S1C88348/317/316/308 TECHNICAL HARDWARE
EPSON
I-i
CONTENTS
Contents
1
INTRODUCTION ............................................................................................. I-1
1.1
Configuration ................................................................................................................... I-1
1.2
Features ........................................................................................................................... I-2
1.3
Block Diagram ................................................................................................................. I-3
1.4
Pin Layout Diagram ........................................................................................................ I-5
2
POWER SUPPLY ............................................................................................. I-13
2.1
Operating Voltage ........................................................................................................... I-13
2.2
Internal Power Supply Circuit ........................................................................................ I-13
2.3
Heavy Load Protection Mode ......................................................................................... I-14
3
CPU AND BUS CONFIGURATION .............................................................. I-15
3.1
CPU ................................................................................................................................ I-15
3.2
Internal Memory ............................................................................................................. I-15
3.2.1 ROM ...................................................................................................................................... I-15
3.2.2 RAM ....................................................................................................................................... I-15
3.2.3 I/O memory ............................................................................................................................ I-15
3.2.4 Display memory ..................................................................................................................... I-16
3.3
Exception Processing Vectors ........................................................................................ I-16
3.4
CC (Customized Condition Flag) ................................................................................... I-16
3.5
Chip Mode ....................................................................................................................... I-17
3.5.1 MCU mode and MPU mode .................................................................................................. I-17
3.5.2 Bus mode ............................................................................................................................... I-17
3.6
External Bus .................................................................................................................... I-21
3.6.1 Data bus ................................................................................................................................ I-21
3.6.2 Address bus ........................................................................................................................... I-21
3.6.3 Read (RD)/write (WR) signals ............................................................................................... I-22
3.6.4 Chip enable (CE) signal ........................................................................................................ I-22
3.6.5 WAIT control ......................................................................................................................... I-24
3.6.6 Bus authority release state .................................................................................................... I-25
4
INITIAL RESET .............................................................................................. I-26
4.1
Initial Reset Factors ........................................................................................................ I-26
4.1.1 RESET terminal ..................................................................................................................... I-27
4.1.2 Simultaneous LOW level input at input port terminals K00–K03 ......................................... I-27
4.1.3 Supply voltage detection (SVD) circuit ................................................................................. I-27
4.1.4 Initial reset sequence ............................................................................................................. I-27
4.2
Initial Settings After Initial Reset .................................................................................... I-28
5
PERIPHERAL CIRCUITS AND THEIR OPERATION ............................... I-29
5.1
I/O Memory Map ............................................................................................................ I-30
5.2
System Controller and Bus Control ................................................................................ I-42
5.2.1 Bus mode settings .................................................................................................................. I-42
5.2.2 Address decoder (CE output) settings ................................................................................... I-44
5.2.3 WAIT state settings ................................................................................................................ I-45
5.2.4 Setting the bus authority release request signal .................................................................... I-45
5.2.5 Stack page setting .................................................................................................................. I-45
5.2.6 Control of system controller .................................................................................................. I-46
5.2.7 Programming notes ............................................................................................................... I-49