S1C88348/317/316/308 TECHNICAL SOFTWARE
EPSON
II-55
10 CLOCK TIMER
Notes
(1) To reset the interrupt factor flag, write "1" into the corresponding flags alone, using the AND or LD
instruction. When the OR logic operation instruction has been used, "1" is written for the interrupt
factor flags that have been set to "1" within the same address and those flags are then clear.
(2) The interrupt flags (I1 and I0) have not been reset in the interrupt processing routine of this program
example, so an interrupt lower than IRQ1 level is disabled at the time of generation. When you wish
to accept the next interrupt after an interrupt has been generated, re-setting of the interrupt flags or
resetting the interrupt factor flag is necessary after due consideration for the nesting level.
(3) When stopping the clock timer by writing "0" into the RUN/STOP control register for the clock timer,
the clock timer count actually stops when it advances one count with the timing synchronized to the
256 Hz input clock. For this reason, when the clock timer stops, if the 32 Hz, 8 Hz, 2 Hz and 1 Hz
interrupt factors are generated, the respective interrupt factor flags are set and if interrupt is enabled,
an interrupt is generated. Thus, you should add an interrupt processing and interrupt factor flag
resetting, if necessary.
(4) In this program example for the clock timer, the vector address setting and program have been
allocated from 003000H for the sake of convenience.
Source List
Control of clock timer
external
user_program
public
clock_init,clock32_intr,clock8_intr,clock2_intr,clock1_intr
;
clock32_vector equ
00001ch
;clock32hz interrupt vector offset
clock8_vector
equ
00001eh
;clock8hz interrupt vector offset
clock2_vector
equ
000020h
;clock2hz interrupt vector offset
clock1_vector
equ
000022h
;clock1hz interrupt vector offset
clock
equ
003000h
;program start address offset
br_io
equ
0ffh
;base reg. address (set i/o area)
clock_mode
equ
00ff40h
;timer mode set reg.
clockd
equ
00ff41h
;timer data
intr_pr0
equ
00ff20h
;interrupt priority reg. 0
intr_en0
equ
00ff22h
;interrupt enable reg. 0
intr_fac0
equ
00ff24h
;interrupt factor flag reg.
;
code
Vector address setting for clock timer interrupt
intr_vectors:
org
intr_vectors+clock32_vector
dw
clock32_intr
;clock 32hz interrupt
;
org
intr_vectors+clock8_vector
dw
clock8_intr
;clock 8hz interrupt
;
org
intr_vectors+clock2_vector
dw
clock2_intr
;clock 2hz interrupt
;
org
intr_vectors+clock1_vector
dw
clock1_intr
;clock 1hz interrupt
;