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參數(shù)資料
| 型號(hào)： | S1C88308D0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, UUC170 |
| 封裝： | DIE-170 |
| 文件頁(yè)數(shù)： | 297/343頁(yè) |
| 文件大小： | 2396K |
| 代理商： | S1C88308D0A0100 |
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S1C88348/317/316/308 TECHNICAL HARDWARE
EPSON
I-45
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (System Controller and Bus Control)
5.2.3 WAIT state settings
In order to insure accessing of external low speed
devices during high speed operations, the
S1C883xx is equipped with a WAIT function which
prolongs access time.
The number of wait states inserted can be selected
from a choice of eight as shown in Table 5.2.3.1 by
means of registers WT0–WT2.
Table 5.2.3.1 Setting the number of WAIT states
5.2.5 Stack page setting
Although the stack area used to evacuate registers
during subroutine calls can be arbitrarily moved to
any area in data RAM using the stack pointer SP, its
page address is set in registers SPP0–SPP7 in I/O
memory.
At initial reset, SPP0–SPP7 are set to "00H" (page 0).
Since the internal RAM is arranged on page 0
(S1C88348/317/316: 00F000H–00F7FFH, S1C88308:
00F000H–00F0FFH), the stack area in single chip
mode is inevitably located in page 0.
In expanded 64K mode where RAM is externally
expanded, stack page is likewise limited to page 0.
In order to place the stack area at the final address
in internal RAM, the stack pointer SP is placed at an
initial setting of "F800H" (S1C88348/317/316) or
"F100H" (S1C88308). (SP is pre-decremented.)
In the expanded 512K mode, to place the stack in
external expanded RAM, set a corresponding page
to SPP0–SPP7. The page addresses to which SPP0–
SPP7 can be set are 00H–27H and must be within a
RAM area.
*
A page is each recurrent 64K division of data
memory beginning at address zero.
*
A state is 1/2 cycles of the clock in length.
WAIT states set in software are inserted between
bus cycle states T3–T4.
Note, however, that WAIT states cannot be inserted
when an internal register and internal memory are
being accessed and when operating with the OSC1
oscillation circuit (see "5.4 Oscillation Circuits and
Operating Mode").
Consequently, WAIT state settings in single chip
mode are meaningless.
With regard to WAIT insertion timing, see Section
3.6.5, "WAIT control".
5.2.4 Setting the bus authority release
request signal
With systems performing DMA transfer, the bus
authority release request signal (BREQ) input
terminal and acknowledge signal (BACK) output
terminal have to be set.
The BREQ input terminal is shared with input port
terminal K11 and the BACK output terminal with
output port terminal R51. At initial reset, these
terminal facilities are set as input port terminal and
output port terminal, respectively. The terminals
can be altered to function as BREQ/BACK termi-
nals by writing a "1" to register EBR.
Since there is no bus authority release function in
the S1C88308, register EBR in the S1C88308 is
usable as a general purpose register with read/
write capabilities.
For details on bus authority release, see "3.6.6 Bus
authority release state" and "S1C88 Core CPU
Manual".
WT2
Number of inserted states
1
0
14
12
10
8
6
4
2
No wait
WT1
1
0
1
0
WT0
1
0
1
0
1
0
1
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S1C88308F0A0100 | MICROCONTROLLER, PQFP160 |
| S1C88348F | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PQFP16 |
| S1C88316D | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC172 |
| S1C88316F | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PQFP16 |
| S1C88409D | 8-BIT, MROM, 8.8 MHz, MICROCONTROLLER, UUC108 |
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參數(shù)描述 |
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| S1C88349 | 制造商:EPSON 制造商全稱:EPSON 功能描述:8-bit Single Chip Microcomputer |
| S1C88649 | 制造商:EPSON 制造商全稱:EPSON 功能描述:8-bit Single Chip Microcomputer |
| S1C88650 | 制造商:EPSON 制造商全稱:EPSON 功能描述:8-bit Single Chip Microcomputer |
| S1C88655 | 制造商:EPSON 制造商全稱:EPSON 功能描述:8-bit Single Chip Microcomputer |
| S1C88816 | 制造商:EPSON 制造商全稱:EPSON 功能描述:8-bit Single Chip Microcomputer |
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