I-68
EPSON
S1C88348/317/316/308 TECHNICAL HARDWARE
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Output Ports)
Table 5.6.6.1(c) Output port control bits
s High impedance control
HZR0L, HZR0H: 00FF70HD0, D1
HZR1L, HZR1H: 00FF70HD2, D3
HZR20–HZR27: 00FF71H
HZR30–HZR37: 00FF72H *1
HZR4L, HZR4H: 00FF70HD4, D5 *2
HZR50, HZR51: 00FF70HD6, D7 *1
Sets the output terminals to a high impedance state.
When "1" is written: High impedance
When "0" is written: Complementary
Reading:
Valid
HZRxx is the high impedance control register
which correspond as shown in Table 5.6.3.1 to the
various output port terminals.
When "1" is set to the HZRxx register, the corre-
sponding output port terminal becomes high
impedance state and when "0" is set, it becomes
complementary output.
At initial reset, this register is set to "0" (complimen-
tary).
*
1 In the S1C88308, HZR35–HZR37 and HZR51 are
general purpose registers with read/write
capabilities.
*
2 HZR4L and HZR4H is 2-bit reserved register, it
can be used as a general purpose register with
read/write capabilities.
s DC output control
R00D–R07D: 00FF73H
R10D–R17D: 00FF74H
R20D–R27D: 00FF75H
R30D–R37D: 00FF76H *1
R40D–R47D: 00FF77H *2
R50D, R51D: 00FF78HD0, D1 *1
Sets the data output from the output port terminal Rxx.
When "1" is written: HIGH level output
When "0" is written: LOW level output
Reading:
Valid
RxxD is the data register for each output port.
When "1" is set, the corresponding output port
terminal switches to HIGH (VDD) level, and when
"0" is set, it switches to LOW (VSS) level.
At initial reset, R50D is set to "0" (LOW level
output), all other registers are set to "1" (HIGH level
output).
The output data registers set for bus signal output
can be used as general purpose registers with read/
write capabilities which do not affect the output
terminals.
*
1 In the S1C88308, R35D–R37D and R51D are
general purpose registers with read/write
capabilities.
*
2 R40D–R47D is 8-bit reserved register, it can be
used as a general purpose register with read/
write capabilities.
Address Bit
Name
00FF40 D7
D6
D5
D4
D3
D2
D1
D0
–
FOUT2
FOUT1
FOUT0
FOUTON
WDRST
TMRST
TMRUN
SR R/W
Function
Comment
–
FOUT frequency selection
FOUT output control
Watchdog timer reset
Clock timer reset
Clock timer Run/Stop control
"0" when being read
Constantly "0" when
being read
10
–
0
–
0
R/W
W
R/W
–
On
Reset
Run
–
Off
No operation
Stop
FOUT2
0
1
FOUT1
0
1
0
1
FOUT0
0
1
0
1
0
1
0
1
Frequency
fOSC1 / 1
fOSC1 / 2
fOSC1 / 4
fOSC1 / 8
fOSC3 / 1
fOSC3 / 2
fOSC3 / 4
fOSC3 / 8