I-48
EPSON
S1C88348/317/316/308 TECHNICAL HARDWARE
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (System Controller and Bus Control)
CE0–CE3: 00FF00HD0–D3
Sets the CE output terminals being used.
When "1" is written: CE output enable
When "0" is written: CE output disable
Reading:
Valid
CE output is enabled when a "1" is written to
registers CE0–CE3 which correspond to the CE
output being used. A "0" written to any of the
registers disables CE signal output from that
terminal and it reverts to its alternate function as an
output port terminal (R30–R33).
At initial reset, register CE0 is set to "0" in the MCU
mode and in the MPU mode, "1" is set in the
register. Registers CE1–CE3 are always set to "0"
regardless of the MCU/MPU mode setting.
Note: To avoid a malfunction from an interrupt
generated before the bus configuration is
initialized, all interrupts including NMI are
masked until you write an optional value into
address "00FF00H".
SPP0–SPP7: 00FF01H
Sets the page address of stack area. In single chip
mode and expanded 64K mode, set page address to
"00H".
In expanded 512K mode, it can be set to any value
within the range "00H"–"27H".
Since a carry and borrow from/to the stack pointer
SP is not reflected in register SPP, the upper limit
on continuous use of the stack area is 64K bytes.
At initial reset, this register is set to "00H" (page 0).
Note: To avoid a malfunction from an interrupt
generated before the bus configuration is
initialized, all interrupts including NMI are
disabled, until you write an optional value
into "00FF01H" address. Furthermore, to
avoid generating an interrupt while the stack
area is being set, all interrupts including NMI
are disabled in one instruction execution
period after writing to address "00FF01H".
BSMD0, BSMD1: 00FF00HD6, D7
Bus modes are set as shown in Table 5.2.6.2.
Table 5.2.6.2 Bus mode settings
The single chip mode setting is only possible when
this IC is used in the MCU mode. The single chip
mode setting is incompatible with the MPU mode,
since this mode does not utilize internal ROM.
When using in the MPU mode, it is necessary to
select the bus mode at the time of the initial reset-
ting and at the time of the <BSMD1 = "0" and
of expanded modes (expanded 64K mode, ex-
panded 512K minimum mode and expanded 512K
maximum mode) by mask option.
Select the expanded 512K maximum mode for this
option, when the MPU mode is not used at all.
At initial reset, in the MCU mode the unit is set to
single chip mode and in the MPU mode the mask
option is used to select the applicable mode.
CEMD0, CEMD1: 00FF00HD4, D5
Sets the CE signal address range (valid only in the
expanded 64K mode).
Settings are made according to external memory
chip size as shown in Table 5.2.6.3.
Table 5.2.6.3 CE signal settings
*
At the case of MPU mode, CE0–CE3.
These settings are invalid for any mode other than
expanded 64K mode.
At initial reset, each register is set to "1" (64K bytes).
BSMD1
Bus mode
1
0
Expanded 512K maximum mode
Expanded 512K minimum mode
Expanded 64K mode
Single chip mode (MCU)
Optional setting of one of the
expanded modes (MPU)
BSMD0
1
0
1
0
Setting values
CEMD1
Usable terminals
1
0
CE0
CE0, CE1
CE0–CE3
CE1–CE3..S1C88316 *
CE0–CE3
CEMD0
1
0
1
0
Address range
64K bytes
32K bytes
16K bytes
8K bytes