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參數(shù)資料
| 型號(hào)： | S1C88308D0A0100 |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, UUC170 |
| 封裝： | DIE-170 |
| 文件頁(yè)數(shù)： | 330/343頁(yè) |
| 文件大?。?/td> | 2396K |
| 代理商： | S1C88308D0A0100 |
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S1C88348/317/316/308 TECHNICAL HARDWARE
EPSON
I-75
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)
5.8.2 Mask option
Since serial interface input/output terminals are
shared with the I/O ports, serial interface terminal
specifications have necessarily been selected with
the mask option for I/O ports.
I/O port pull-up resistors
P10 (SIN) ........ s
s With resistor s
s Gate direct
P12 (SCLK) .... s
s With resistor s
s Gate direct
Each I/O port terminal is equipped with a pull-up
resistor which goes ON in input mode. A selection
can be made for each port (one bit unit) as to
whether or not the resistor will be used.
Specifications (whether the pull-up will be used or
not) of P10 (SIN) and P12 (SCLK) which will become
input terminals when using the serial interface are
decided by settings the options for the I/O port.
When "Gate direct" is selected in the serial I/F
mode, be sure that the input terminals do not go
into a floating state.
5.8.3 Transfer modes
There are four transfer modes for the serial inter-
face and mode selection is made by setting the two
bits of the mode selection registers SMD0 and
SMD1 as shown in the table below.
Table 5.8.3.1 Transfer modes
At initial reset, transfer mode is set to clock syn-
chronous master mode.
s Clock synchronous master mode
In this mode, the internal clock is utilized as a
synchronous clock for the built-in shift registers,
and clock synchronous 8-bit serial transfers can be
performed with this serial interface as the master.
Table 5.8.3.2 Terminal settings corresponding
to each transfer mode
The synchronous clock is also output from the
SCLK terminal which enables control of the
external (slave side) serial I/O device. Since the
SRDY terminal is not utilized in this mode, it can be
used as an I/O port.
Figure 5.8.3.1(a) shows the connection example of
input/output terminals in the clock synchronous
master mode.
s Clock synchronous slave mode
In this mode, a synchronous clock from the external
(master side) serial input/output device is utilized
and clock synchronous 8-bit serial transfers can be
performed with this serial interface as the slave.
The synchronous clock is input to the SCLK
terminal and is utilized by this interface as the
synchronous clock.
Furthermore, the SRDY signal indicating the
transmit-receive ready status is output from the
SRDY terminal in accordance with the serial
interface operating status.
In the slave mode, the settings for registers SCS0
and SCS1 used to select the clock source are invalid.
Figure 5.8.3.1(b) shows the connection example of
input/output terminals in the clock synchronous
slave mode.
s Asynchronous 7-bit mode
In this mode, asynchronous 7-bit transfer can be
performed. Parity check during data reception and
addition of parity bit (odd/even/none) during
transmitting can be specified and data processed in
7 bits with or without parity. Since this mode
employs the internal clock, the SCLK terminal is
not used. Furthermore, since the SRDY terminal is
not utilized either, both of these terminals can be
used as I/O ports.
Figure 5.8.3.1(c) shows the connection example of
input/output terminals in the asynchronous mode.
s Asynchronous 8-bit mode
In this mode, asynchronous 8-bit transfer can be
performed. Parity check during data reception and
addition of parity bit (odd/even/none) during
transmitting can be specified and data processed in
8 bits with or without parity. Since this mode
employs the internal clock, the SCLK terminal is
not used. Furthermore, since the SRDY terminal is
not utilized either, both of these terminals can be
used as I/O ports.
Figure 5.8.3.1(c) shows the connection example of
input/output terminals in the asynchronous mode.
SMD1
SMD0
Mode
1
0
1
0
1
0
Asynchronous 8-bit
Asynchronous 7-bit
Clock synchronous slave
Clock synchronous master
Mode
SIN
Asynchronous 8-bit
Asynchronous 7-bit
Clock synchronous slave
Clock synchronous master
P13
Output
P13
SOUT SCLK
SRDY
P12
Input
Output
Input
相關(guān)PDF資料 |
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| S1C88308F0A0100 | MICROCONTROLLER, PQFP160 |
| S1C88348F | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PQFP16 |
| S1C88316D | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC172 |
| S1C88316F | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PQFP16 |
| S1C88409D | 8-BIT, MROM, 8.8 MHz, MICROCONTROLLER, UUC108 |
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