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參數(shù)資料
| 型號： | S1C88104P0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PBGA240 |
| 封裝： | VFBGA10H-216 |
| 文件頁數(shù)： | 47/211頁 |
| 文件大?。?/td> | 1802K |
| 代理商： | S1C88104P0A0100 |
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132
EPSON
S1C8F626 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Interrupt and Standby Status)
5.14.4 Interrupt priority register and interrupt priority level
Table 5.14.4.1 Interrupt priority register
Interrupt
K00–K07 input interrupt
Programmable timer interrupt 1–0
Programmable timer interrupt 3–2
Programmable timer interrupt 5–4
Programmable timer interrupt 7–6
Serial interface 0 interrupt
Serial interface 1 interrupt
Stopwatch timer interrupt
Clock timer interrupt
Interrupt priority register
PK00, PK01
PPT0, PPT1
PPT2, PPT3
PPT4, PPT5
PPT6, PPT7
PSIF00, PSIF01
PSIF10, PSIF11
PSW0, PSW1
PTM0, PTM1
00FF20D6, D7
00FF21D2, D3
00FF21D4, D5
00FF2AD0, D1
00FF2AD2, D3
00FF20D4, D5
00FF21D0, D1
00FF20D2, D3
00FF20D0, D1
The interrupt priority registers shown in Table
5.14.4.1 are set to each system of interrupts and the
interrupt priority levels for the CPU can be set to
the optional priority level (0–3). As a result, it is
possible to have multiple interrupts that match the
system's interrupt processing priority levels.
The interrupt priority level between each system
can optionally be set to three levels by the interrupt
priority register. However, when more than one
system is set to the same priority level, they are
processed according to the default priority level.
Table 5.14.4.2 Setting of interrupt priority level
P*1P*0
Interrupt priority level
1
0
1
0
1
0
Level 3
(IRQ3)
Level 2
(IRQ2)
Level 1
(IRQ1)
Level 0
(None)
At initial reset, the interrupt priority registers are
all set to "0" and each interrupt is set to level 0.
Furthermore, the priority levels in each system
have been previously decided and they cannot be
changed.
The CPU can mask each interrupt by setting the
interrupt flags (I0 and I1). The relation between the
interrupt priority level of each system and interrupt
flags is shown in Table 5.14.4.3, and the CPU
accepts only interrupts above the level indicated by
the interrupt flags.
The NMI (watchdog timer) that has level 4 priority,
is always accepted regardless of the setting of the
interrupt flags.
Table 5.14.4.3 Interrupt mask setting of CPU
I1
I0
Acceptable interrupt
1
0
1
0
1
0
Level 4 (NMI)
Level 4, Level 3 (IRQ3)
Level 4, Level 3, Level 2 (IRQ2)
Level 4, Level 3, Level 2, Level 1 (IRQ1)
After an interrupt has been accepted, the interrupt
flags are written to the level of that interrupt.
However, interrupt flags after an NMI has been
accepted are written to level 3 (I0 = I1 = "1").
Table 5.14.4.4 Interrupt flags after acceptance of interrupt
I1
I0
Accepted interrupt priority level
1
0
1
0
1
Level 4
(NMI)
Level 3
(IRQ3)
Level 2
(IRQ2)
Level 1
(IRQ1)
The set interrupt flags are reset to their original
value on return from the interrupt processing
routine. Consequently, multiple interrupts up to 3
levels can be controlled by the initial settings of the
interrupt priority registers alone. Additional
multiplexing can be realized by rewriting the
interrupt flags and interrupt enable register in the
interrupt processing routine.
Note: Beware. If the interrupt flags have been
rewritten (set to lower priority) prior to
resetting an interrupt factor flag after an
interrupt has been generated, the same
interrupt will be generated again.
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