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參數(shù)資料
| 型號(hào)： | S1C88104P0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PBGA240 |
| 封裝： | VFBGA10H-216 |
| 文件頁數(shù)： | 194/211頁 |
| 文件大?。?/td> | 1802K |
| 代理商： | S1C88104P0A0100 |
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S1C8F626 TECHNICAL MANUAL
EPSON
75
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)
PSIF00, PSIF01: 00FF21HD0, D1
PSIF10, PSIF11: 00FF21HD2, D3
Sets the priority level of the serial interface inter-
rupt.
The two bits PSIFx0 and PSIFx1 are the interrupt
priority register corresponding to the serial inter-
face interrupt. Table 5.7.10.4 shows the interrupt
priority level which can be set by this register.
Table 5.7.10.4 Interrupt priority level settings
PSIFx1
PSIFx0
Interrupt priority level
1
0
1
0
1
0
Level 3 (IRQ3)
Level 2 (IRQ2)
Level 1 (IRQ1)
Level 0 (None)
At initial reset, this register is set to "0" (level 0).
ESTRA0, ESREC0, ESERR0: 00FF24HD0, D1, D2
ESTRA1, ESREC1, ESERR1: 00FF24HD4, D5, D6
Enables or disables the generation of an interrupt
for the CPU.
When "1" is written: Interrupt enabled
When "0" is written: Interrupt disabled
Reading:
Valid
ESTRAx, ESRECx and ESERRx are interrupt enable
registers that respectively correspond to the
interrupt factors for transmitting complete, receiv-
ing complete and receiving error. Interrupts set to
"1" are enabled and interrupts set to "0" are dis-
abled.
At initial reset, this register is set to "0" (interrupt
disabled).
FSTRA0, FSREC0, FSERR0: 00FF27HD0, D1, D2
FSTRA1, FSREC1, FSERR1: 00FF27HD4, D5, D6
Indicates the serial interface interrupt generation
status.
When "1" is read:
Interrupt factor present
When "0" is read:
Interrupt factor not present
When "1" is written: Resets factor flag
When "0" is written: Invalid
FSTRAx, FSRECx and FSERRx are interrupt factor
flags that respectively correspond to the interrupts
for transmitting complete, receiving complete and
receiving error and are set to "1" by generation of
each factor.
Transmitting complete interrupt factor is generated
at the point where the data transmitting of the shift
register has been completed.
Receiving complete interrupt factor is generated at
the point where the received data has been trans-
ferred into the received data buffer.
Receive error interrupt factor is generated when a
parity error, framing error or overrun error has
been detected during data receiving.
When set in this manner, if the corresponding
interrupt enable register is set to "1" and the
corresponding interrupt priority register is set to a
higher level than the setting of interrupt flags (I0
and I1), an interrupt will be generated to the CPU.
Regardless of the interrupt enable register and
interrupt priority register settings, the interrupt
factor flag will be set to "1" by the occurrence of an
interrupt generation condition.
To accept the subsequent interrupt after interrupt
generation, re-setting of the interrupt flags (set
interrupt flag to lower level than the level indicated
by the interrupt priority registers, or execute the
RETE instruction) and interrupt factor flag reset are
necessary. The interrupt factor flag is reset to "0" by
writing "1".
At initial reset, this flag is reset to "0".
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