S1C8F626 TECHNICAL MANUAL
EPSON
29
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (System Controller)
5.2 System Controller
The system controller is a management unit that
controls memory access according to the CPU
mode. The following conditions must be set with
software according to the program area size:
(1) CPU mode
(2) Page address of the stack pointer
Below is a description of the how these settings are
to be made.
Note: It is not necessary to change the initialized
values when the S1C8F626 is used in
minimum CPU mode. However, to clear the
interrupt mask that was set at initial reset to
disable all interrupts, data must be written to
the addresses (FF00H and FF01H) of the
system controller registers.
5.2.1 Setting the CPU mode
The S1C8F626 has two CPU modes (minimum
mode and maximum mode) and it should be set
according to the program size using the CPUMOD
register.
Minimum mode (CPUMOD = "0")
Use the IC in minimum mode when the
program size is less than 64K bytes and the
program area described below is used.
Configuration 1: ROM area 1 (48K bytes from
0H to BFFFH) only is used
Bank 0 (0H to 7FFFH) and Bank 1 (8000H to
BFFFH) are used in this configuration, so set
1 (Bank 1) to the CB register.
Configuration 2: Bank 0 in ROM area 1 (32K
bytes from 0H to 7FFFH) and one bank (32K
bytes) in ROM area 2 (10000H to 3FFFFH) are
used
Set the bank number (one of 2 to 7) to be
used as a program area to the CB register.
In this configuration, Bank 1 (16K bytes in
ROM area 1, 8000H to BFFFH) cannot be
used as a program area.
This mode does not save the CB register
contents on the stack when a subroutine is
called. It makes it possible to economize on
stack area usage.
Maximum mode (CPUMOD = "1")
The entire ROM can be used as a program area
in this mode, note, however, that the CB register
must be modified every time the program
sequence moves to another bank from the
currently executed bank to access areas
exceeding 64K bytes. The maximum mode saves
the CB register contents on the stack when a
subroutine is called.
5.2.2 Setting the stack page
By using the stack pointer SP, any area in the RAM
can be allocated to the stack used to save register
contents when subroutines are called. However, the
stack page address must be set using the SPP0–
SPP7 registers in the I/O memory.
The SPP0–SPP7 registers are set to "00H" (page 0) at
initial reset and this IC does not need to change the
address. However, write "00H" to these registers
after an initial reset to clear interrupt mask.
To place the stack area at the end of the internal
RAM, the stack pointer SP should be initialized to
"F800H". (SP is pre-decremented.)
A page is each recurrent 64K division of data
memory beginning at address zero.