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參數(shù)資料
| 型號： | S1C88104P0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, PBGA240 |
| 封裝： | VFBGA10H-216 |
| 文件頁數(shù)： | 19/211頁 |
| 文件大?。?/td> | 1802K |
| 代理商： | S1C88104P0A0100 |
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S1C8F626 TECHNICAL MANUAL
EPSON
107
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)
ETU0: 00FF25HD0
ETU1: 00FF25HD2
ETU2: 00FF25HD4
ETU3: 00FF25HD6
ETU4: 00FF2CHD0
ETU5: 00FF2CHD2
ETU6: 00FF2CHD4
ETU7: 00FF2CHD6
Enables or disables the underflow interrupt
generation to the CPU.
When "1" is written: Interrupt is enabled
When "0" is written: Interrupt is disabled
Reading:
Valid
The ETUx register is the interrupt enable register
corresponding to the underflow interrupt factor of
Timer x.
Interrupt in which the ETUx register is set to "1" is
enabled, and the others in which the ETUx register
is set to "0" are disabled.
In the 16-bit mode, the setting of the ETU(L) is
invalid.
At initial reset, this register is set to "0" (interrupt
is disabled).
ETC0: 00FF25HD1
ETC1: 00FF25HD3
ETC2: 00FF25HD5
ETC3: 00FF25HD7
ETC4: 00FF2CHD1
ETC5: 00FF2CHD3
ETC6: 00FF2CHD5
ETC7: 00FF2CHD7
Enables or disables the compare match interrupt
generation to the CPU.
When "1" is written: Interrupt is enabled
When "0" is written: Interrupt is disabled
Reading:
Valid
The ETCx register is the interrupt enable register
corresponding to the compare match interrupt
factor of Timer x.
Interrupt in which the ETCx register is set to "1" is
enabled, and the others in which the ETCx register
is set to "0" are disabled.
In the 16-bit mode, the setting of the ETC(L) is
invalid.
At initial reset, this register is set to "0" (interrupt
is disabled).
FTU0: 00FF29HD0
FTU1: 00FF29HD2
FTU2: 00FF29HD4
FTU3: 00FF29HD6
FTU4: 00FF2EHD0
FTU5: 00FF2EHD2
FTU6: 00FF2EHD4
FTU7: 00FF2EHD6
Indicates the generation of underflow interrupt
factor.
When "1" is read:
Int. factor has generated
When "0" is read:
Int. factor has not generated
When "1" is written: Factor flag is reset
When "0" is written: Invalid
FTUx is the interrupt factor flag corresponding to
interrupt of Timer x, and is set to "1" due to the
counter underflow.
At this point, if the corresponding interrupt enable
register is set to "1" and the corresponding inter-
rupt priority register is set to a higher level than
the setting of the interrupt flags (I0 and I1), an
interrupt is generated to the CPU.
Regardless of the interrupt enable register and
interrupt priority register settings, the interrupt
factor flag is set to "1" when the interrupt genera-
tion condition is met.
To accept the subsequent interrupt after an
interrupt generation, it is necessary to re-set the
interrupt flags (set the interrupt flag to a lower
level than the level indicated by the interrupt
priority registers, or execute the RETE instruction)
and to reset the interrupt factor flag. The interrupt
factor flag is reset to "0" by writing "1".
In the 16-bit mode, the interrupt factor flag FTU(L)
is not set to "1" and Timer(L) interrupt is not
generated. In this mode, the interrupt factor flag
FTU(H) is set to "1" by the underflow of the 16-bit
counter.
At initial reset, this flag is reset to "0".
FTC0: 00FF29HD1
FTC1: 00FF29HD3
FTC2: 00FF29HD5
FTC3: 00FF29HD7
FTC4: 00FF2EHD1
FTC5: 00FF2EHD3
FTC6: 00FF2EHD5
FTC7: 00FF2EHD7
Indicates the generation of compare match inter-
rupt factor.
When "1" is read:
Int. factor has generated
When "0" is read:
Int. factor has not generated
When "1" is written: Factor flag is reset
When "0" is written: Invalid
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