參數(shù)資料
型號: RTL8305SB
英文描述: RTL8305SB
中文描述: RTL8305SB
文件頁數(shù): 64/66頁
文件大小: 963K
代理商: RTL8305SB
12. Design and Layout Guide
RTL8305SB
2002/04/09
64
Rev.1.0
In order to achieve maximum performance using the RTL8305SB, good design attention is required throughout the design and
layout process. The following are some suggestions on recommendations to implement a high performance system.
General Guidelines
Provide a good power source, minimizing noise from switching power supply circuits (<50mV).
Verify the qualities of critical components such as clock source and transformer to meet application requirements.
Keep power and ground noise levels below 50mV.
Use bulk capacitors (4.7μF-10μF) between the power and ground planes.
Use 0.1μF de-coupling capacitors to reduce high-frequency noise on the power and ground planes.
Keep de-coupling capacitors as close as possible to the RTL8305SB chip.
Differential Signal Layout Guidelines
Keep differential pairs as close as possible and route both traces as identically as possible.
Avoid vias and layer changes if possible.
Keep transmit and receive pairs away from each other. Run orthogonal or separate by a ground plane.
Clock Circuit
Surround the clock by ground trace to minimize the high-frequency emission, if possible.
2.5V Power
Do not connect a bead directly between the collector of the PNP transistor and VDDAL. This will significantly affect the
stability of the 2.5V power if such a bead is used.
Use a bulk capacitor (4.7μF-10μF) between the collector of the PNP transistor and the ground plane.
Do not use one PNP transistor for more than one RTL8305SB chip, even if the rating is enough. Use one transistor for each
RTL8305SB chip.
Power Planes
Divide the power plane into 2.5V digital, and 3.3V analog.
Use 0.1μF decoupling capacitors and bulk capacitors between each power plane and the ground plane.
Ground Planes
Keep the system ground region as one continuous, unbroken plane that extends from the primary side of the transformer to
the rest of the board.
Place a moat (gap) between the system ground and chassis ground.
Ensure the chassis ground area is voided at some point such that no ground loop exists on the chassis ground area.
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