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參數(shù)資料
| 型號： | RTL8305SB |
| 英文描述： | RTL8305SB |
| 中文描述： | RTL8305SB |
| 文件頁數(shù)： | 12/66頁 |
| 文件大?。?/td> | 963K |
| 代理商： | RTL8305SB |
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RTL8305SB
2002/04/09
12
Rev.1.0
P4SPDSTA/
P4SPD100
47
I
Port4 Speed Status:
Port4 initial configuration pin for Speed upon reset
for PHY of UTP mode only and Speed Status for MAC of other mode in
real time after reset.
1: 100Mbps
0: 10Mbps
When P4MODE[1:0]=11 (UTP/MAC mode MII), this pin provides the
initial configuration of speed for the PHY part upon reset (UTP) then
determines speed status of MAC mode MII in real time after reset. The
speed status of the PHY part (UTP) is provided by the internal PHY in
real time after reset.
When P4MODE[1:0]=10 (100Base-FX mode), speed is dedicated to
100M. This pin does nothing and should be left floating.
When P4MODE[1:0]=01 (PHY mode MII), this pin determines the
duplex status of Port4 in real time after reset.
When P4MODE[1:0]=00 (PHY mode SNI), speed is dedicated to
10MHz clock rate. This pin should be pulled down.
For the application listed below, this pin should be left floating:
For P4MODE[1:0]=10 (100Base-FX mode).
For the application listed below, this pin should be pulled down:
For PHY mode SNI, speed is dedicated to 10MHz clock rate.
8305SB = P4SPDSTA/P4SPD100, 8305S = P4SPDSTA#.
In order to provide 100M for the default value for PHY, this pin is
changed as high active.
Port4 Flow Control:
Port4 initial configuration pin for Flow Control
upon reset for PHY of UTP and FX mode and Flow Control Status for
MAC of other mode in real time after reset.
1=Enable Flow Control ability.
0=Disable Flow Control ability.
When P4MODE[1:0]=11 (UTP/MAC mode MII), this pin provides the
initial configuration of flow control for the PHY part upon reset (UTP)
then determines the flow control status of MAC mode MII in real time
after reset. The flow control status of PHY part (UTP) is provided by the
internal PHY in real time after reset.
When P4MODE[1:0]=10 (100Base-FX mode), this pin provides the
initial configuration of flow control for the PHY part upon reset (FX).
When P4MODE[1:0]=01 (PHY mode MII), this pin determines the
duplex status of Port4 in real time after reset.
When P4MODE[1:0]=00 (PHY mode SNI), flow control should be
disabled. This pin should be pulled down.
8305SB = P4FLCTRL/P4EnFC, 8305S = P4FLCTRL#.
In order to enable flow control ability for the PHY, this pin is changed as
high active.
1
P4FLCTRL/
P4EnFC
46
I
1
Cont…
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