參數(shù)資料
型號： RJ80530VZ733256
英文描述： Microprocessor
中文描述： 微處理器
文件頁數(shù)： 40/89頁
文件大?。?/td> 1672K
代理商： RJ80530VZ733256
Mobile Intel
Pentium
III Processor-M Datasheet
40
Datasheet
298340-002
Table 27. TAP Signal AC Specifications
1
Symbol
Parameter
Min
Max Unit
Figure
Notes
T30
TCK Frequency
—
16.67 MHz
T31
TCK Period
60
—
ns
6
T32
TCK High Time
25.0
ns
6
≥
V
CMOSREF
+0.2V, Note 2
T33
TCK Low Time
25.0
ns
6
≤
V
CMOSREF
-0.2V, Note 2
(V
CMOSREF
-0.2V) –
(V
+0.2V),
Notes 2, 3
T34
TCK Rise Time
5.0
ns
6
T35
TCK Fall Time
5.0
ns
6
(V
CMOSREF
+0.2V) –
(V
-0.2V) ,
Notes 2, 3
T36
TRST# Pulse Width
40.0
ns
16
Asynchronous, Note 2
T37
TDI, TMS Setup Time
5.0
ns
15
Note 4
T38
TDI, TMS Hold Time
14.0
ns
15
Note 4
T39
TDO Valid Delay
1.0
10.0
ns
15
Notes 5, 6
T40
TDO Float Delay
25.0
ns
15
Notes 2, 5, 6
T41
All Non-Test Outputs Valid Delay
2.0
25.0
ns
15
Notes 5, 7, 8
T42
All Non-Test Outputs Float Delay
25.0
ns
15
Notes 2, 5, 7, 8
T43
All Non-Test Inputs Setup Time
5.0
ns
15
Notes 4, 7, 8
T44
NOTES:
1.
All AC timings for TAP signals are referenced to the TCK rising edge at 1.0V. All TAP and CMOS signals are
referenced at 1.0V.
2.
Not 100% tested. Specified by design/characterization.
3.
1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16 MHz.
4.
Referenced to TCK rising edge.
5.
Referenced to TCK falling edge.
6.
Valid delay timing for this signal is specified into 150
terminated to 1.5V and 0 pF of external load. For real
system timings these specifications must be derated for external capacitance at 105 ps/pF.
7.
Non-Test Outputs and Inputs are the normal output or input signals (except TCK, TRST#, TDI, TDO, and TMS).
These timings correspond to the response of these signals due to boundary scan operations.
8.
During Debug Port operation use the normal specified timings rather than the TAP signal timings.
All Non-Test Inputs Hold Time
13.0
ns
15
Notes 4, 7, 8
Table 28. Quick Start/Deep Sleep AC Specifications
1
Symbol
Parameter
Min Max
Unit
Figure
Notes
T45
Quick Start Cycle Completion to Clock Stop or
DPSLP# assertion
100
BCLKs 17, 18
T46
Quick Start Cycle Completion to Input Signals Stable
0
μ
s
17, 18
T47
Deep Sleep PLL Lock Latency
0
30
μ
s
ns
17, 18
Note 2
T48
STPCLK# Hold Time from PLL Lock
0
17, 18
T49
NOTES:
1.
Input signals other than RESET# and BPRI# must be held constant in the Quick Start state.
2.
The BCLK, BCLK# Settling Time specification (T60) applies to Deep Sleep state exit under all conditions.
Input Signal Hold Time from STPCLK# Deassertion
8
BCLKs 17, 18
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