參數(shù)資料
型號(hào)： RH80530NZ009256
英文描述： MICROPROCESSOR|32-BIT|CMOS|PGA|478PIN|CERAMIC
中文描述： 微處理器| 32位|的CMOS |美巡賽| 478PIN |陶瓷
文件頁(yè)數(shù)： 22/89頁(yè)
文件大?。?/td> 1672K
代理商： RH80530NZ009256
Mobile Intel
Pentium
III Processor-M Datasheet
22
Datasheet
298340-002
3.1.5.2
CMOS and Open-drain Signals
The CMOS input signals are allowed to be in either the logic high or low state when the processor is in
a low-power state. In the Auto Halt state these signals are allowed to toggle. These input buffers have
no internal pull-up or pull-down resistors and system logic can use CMOS or Open-drain drivers to
drive them.
The Open-drain output signals have open drain drivers and external pull-up resistors are required. One
of the two output signals (IERR#) is a catastrophic error indicator and is tri-stated (and pulled-up)
when the processor is functioning normally. The FERR# output can be either tri-stated or driven to V
SS
when the processor is in a low-power state depending on the condition of the floating-point unit. Since
this signal is a DC current path when it is driven to V
SS
, Intel recommends that the software clears or
masks any floating-point error condition before putting the processor into the Deep Sleep state.
3.1.5.3
Other Signals
The system bus clocks (BCLK, BCLK#) must be driven in all of the low-power states except the Deep
Sleep state. The APIC clock (PICCLK) must be driven whenever BCLK and BCLK# are driven.
Otherwise, it is permitted to turn off PICCLK by holding it at V
SS
. BCLK and BCLK# should be obey
the DC levels in Table 30(for Differential Clocking) and Table 31 (for Single Ended Clocking).
In the Auto Halt state, the APIC bus data signals (PICD[1:0]) may toggle due to APIC bus messages.
These signals are required to be tri-stated and pulled-up when the processor is in the Quick Start or
Deep Sleep states.
3.2
Power Supply Requirements
3.2.1
Decoupling Guidelines
The Mobile Intel Pentium
III
Processor-M Micro-FCPGA package has twelve 0805IDC, 1-
μ
F surface
mount decoupling capacitors. Eight capacitors are on the V
CC
supply and four capacitors are on V
CCT.
For the Micro-FCBGA package, there are six 0.68-
μ
F capacitors on V
CC
and two 0.68-
μ
F capacitors
on V
CCT
. In addition to the package capacitors, sufficient board level capacitors are also necessary for
power supply decoupling. These guidelines are as follows:
High and Mid Frequency VCC decoupling – Place twenty-four 0.22-
μ
F 0603 capacitors directly
under the package on the solder side of the motherboard using at least two vias per capacitor
node. Ten 10-
μ
F X7 6.3V 1206-size ceramic capacitors should be placed around the package
periphery near the balls. Trace lengths to the vias should be designed to minimize inductance.
Avoid bending traces to minimize ESL.
High and Mid Frequency VCCT decoupling – Place ten 1-
μ
F X7R 0603 ceramic capacitors close
to the package. Via and trace guidelines are the same as above.
Bulk VCC decoupling – Minimum of 1200
μ
F capacitance with Equivalent Series Resistance
(ESR) less than or equal to 3.5 m
.
Bulk VCCT decoupling – Platform dependent but recommendation for Intel
830 Chipset Family
based systems is minimum of 660
μ
F with ESR less than or equal to 7 m
.
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相關(guān)代理商/技術(shù)參數(shù)
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