參數(shù)資料
型號(hào)： RD28F6408W30T85
廠商： INTEL CORP
元件分類： 存儲(chǔ)器
英文描述： 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30)
中文描述： SPECIALTY MEMORY CIRCUIT, PBGA80
封裝： 14 X 8 MM, 0.80 MM PITCH, STACK, CSP-80
文件頁(yè)數(shù)： 24/82頁(yè)
文件大?。?/td> 749K
代理商： RD28F6408W30T85
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
18
Preliminary
As an example, a clock frequency of 52 MHz will be used. The clock period is 19.2 ns. This data is
applied to the formula above for the subsequent reads assuming the data output hold time is one
clock:
14 ns + 4 ns
≤
19.2 ns
This equation is satisfied and data output will be available and valid at every clock period.
If t
DATA
is long, hold for two cycles.
Now assume the clock frequency is 66 MHz. This corresponds to a 15 ns period. The initial access
time is calculated to be 80 ns (LC 4). This condition satisfies t
AVQV
(ns) + t
ADD-DELAY
(ns) +
t
DATA
(ns) = 70 ns + 6 ns + 4 ns = 80 ns, as shown above in the First Access Latency Count
equations. However, the data output hold time of one clock violates the one-clock data hold
condition:
t
CHQV
(ns) + t
DATA
(ns)
≤
One CLK Period
14 ns + 4 ns = 18 ns is not less than one clock period of 15 ns. To satisfy the formula above, the
data output hold time must be set at 2 clocks to correctly allow for data output setup time. This
formula is also satisfied if the CPU has t
DATA
(ns)
≤
1 ns, which yields:
14 ns + 1 ns
≤
15 ns
In page mode reads, the initial access time can be determined by the formula:
t
ADD-DELAY
(ns) + t
DATA
(ns) + t
AVQV
(ns)
and subsequent reads in page mode are defined by:
t
APA
(ns) + t
DATA
(ns)
(minimum time)
4.2.6
WAIT Configuration (WC)
CR.8 sets the WAIT signal delay. The WAIT signal delay determines when the WAIT signal is
asserted. The WAIT signal can be asserted either one clock before or at the time of the misaligned
16-word boundary crossing. An asserted WAIT signal indicates invalid data on the data bus.
Figure 8. Data Output Configuration with WAIT Signal Delay
DQ
15-0
[Q]
CLK [C]
Valid
Output
Valid
Output
Valid
Output
DQ
15-0
[Q]
Valid
Output
Valid
Output
1 CLK
Data Hold
WAIT (CR.8 = 1)
WAIT (CR.8 = 0)
t
CHQV
t
CHQV
WAIT (CR.8 = 0)
WAIT (CR.8 = 1)
2 CLK
Data Hold
t
CHTL/H
Note 1
Note 1
Note 1
Note 1
Note1: WAIT shown active high (CR.10 = 1)
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