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參數(shù)資料
| 型號： | PF38F40L0YUQ0 |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 16M X 16 FLASH 1.8V PROM, PBGA88 |
| 封裝： | 8 X 11 MM, 1 MM HEIGHT, ROHS COMPLIANT, VFBGA-88 |
| 文件頁數(shù)： | 64/99頁 |
| 文件大小： | 1419K |
| 代理商： | PF38F40L0YUQ0 |
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Intel StrataFlash Wireless Memory (L18) with A/D-Multiplexed I/O
July 2006
Datasheet
Order Number: 313295-002US
67
Intel StrataFlash Wireless Memory (L18)
14.2.2.3
Write Operation with Clock Active
W21 - t
VHWL
W22 - t
CHWL
The AC parameters W21 (tVHWL- ADV# High to WE# Low) and W22 (tCHWL -Clock high
to WE# low) are required when the device is in a synchronous mode and clock is active.
A write bus cycle consists of two parts:
the host provides an address to the flash device; and
the host then provides data to the flash device.
The flash device in turn binds the received data with the received address. When
operating synchronously (RCR.15 = 0), the address of a write cycle may be provided to
the flash by the first active clock edge with ADV# low, or rising edge of ADV# as long
as the applicable cycle separation conditions are met between each cycle.
If neither a clock edge nor a rising ADV# edge is used to provide a new address at the
beginning of a write cycle (the clock is stopped and ADV# is low), the address may also
be provided to the flash device by holding the address bus stable for the required
amount of time (W5, tAVWH) before the rising WE# edge.
Alternatively, the host may choose not to provide an address to the flash device during
subsequent write cycles (if ADV# is high and only CE# or WE# is toggled to separate
the prior cycle from the current write cycle). In this case, the flash device will use the
most recently provided address from the host.
Read” on page 32, for representation of these timings.
14.2.3
Read Operation During Buffered Programming Flowchart
The multi-partition architecture of the device allows background programming (or
erasing) to occur in one partition while data reads (or code execution) take place in
another partition.
To perform a read while buffered programming operation, first issue a Buffered
Program set up command in a partition. When a read operation occurs in the same
partition after issuing a setup command, Status Register data will be returned,
regardless of the read mode of the partition prior to issuing the setup command.
To read data from a block in other partition and the other partition already in read array
mode, a new block address must be issued. However, if the other partition is not
already in read array mode, issuing a read array command will cause the buffered
program operation to abort and a command sequence error would be posted in the
Status Register. See Figure 33, “Buffer Program Flowchart” on page 81 for more
details.
Note:
Simultaneous read-while-Buffered EFP is not supported.
14.2.4
Simultaneous Operation Restrictions
The Protection Registers share some of the same internal flash resources as the
parameter partition. Therefore, simultaneous read-while-write is only allowed between
the protection register and main partitions. Table 21 describes the operation allowed
using read-while-write/erase with the protection register.
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