參數(shù)資料
型號(hào)： PF38F40L0YUQ0
廠商： NUMONYX
元件分類： PROM
英文描述： 16M X 16 FLASH 1.8V PROM, PBGA88
封裝： 8 X 11 MM, 1 MM HEIGHT, ROHS COMPLIANT, VFBGA-88
文件頁數(shù)： 49/99頁
文件大小： 1419K
代理商： PF38F40L0YUQ0
Intel StrataFlash Wireless Memory (L18) with A/D-Multiplexed I/O
July 2006
Datasheet
Order Number: 313295-002US
53
Intel StrataFlash Wireless Memory (L18)
11.1.1
Factory Word Programming
Factory word programming is similar to word programming in that it uses the same
commands and programming algorithms. However, factory word programming
enhances the programming performance with VPP = VPPH. This can enable faster
programming times during OEM manufacturing processes. Factory word programming
is not intended for extended use. See Section 5.2, “Operating Conditions” on page 19
for limitations when VPP = VPPH.
Note:
When VPP = VPPL, the device draws programming current from the VCC supply. If VPP is
driven by a logic signal, VPPL must remain above VPPL MIN to program the device. When
VPP = VPPH, the device draws programming current from the VPP supply. Figure 19,
“Example VPP Supply Connections” on page 57 shows examples of device power supply
configurations.
11.2
Buffered Programming
The device features a 32-word buffer to enable optimum programming performance.
For buffered programming, data is first written to an on-chip write buffer. Then the
buffer data is programmed into the flash memory array in buffer-size increments. This
can improve system programming performance significantly over non-buffered
programming.
When the Buffered Programming Setup command is issued (see Section 9.2, “Device
Commands” on page 40), Status Register information is updated and reflects the
availability of the write buffer. SR[7] indicates buffer availability: if set, the buffer is
available; if cleared, the write buffer is not available. To retry, issue the Buffered
Programming Setup command again, and re-check SR[7]. When SR[7] is set, the
buffer is ready for loading. (see Figure 33, “Buffer Program Flowchart” on page 81).
On the next write, a word count is written to the device at the buffer address. This tells
the device how many data words will be written to the buffer, up to the maximum size
of the buffer.
On the next write, a device start address is given along with the first data to be written
to the flash memory array. Subsequent writes provide additional device addresses and
data. All data addresses must lie within the start address plus the word count.
Optimum programming performance and lower power usage are obtained by aligning
the starting address at the beginning of a 32-word boundary (A[4:0] = 0x00). Crossing
a 32-word boundary during programming will double the total programming time.
After the last data is written to the buffer, the Buffered Programming Confirm command
is issued to the original block address. The WSM begins to program buffer contents to
the flash memory array. If a command other than the Buffered Programming Confirm
command is written to the device, a command sequence error occurs and Status
Register bits SR[7,5,4] are set. If an error occurs while writing to the array, the device
stops programming, and Status Register bits SR[7,4] are set, indicating a programming
failure.
Reading from another partition is allowed while data is being programmed into the
Additional buffer writes can be initiated by issuing another Buffered Programming
Setup command and repeating the buffered program sequence. Buffered programming
may be performed with VPP = VPPL or VPPH (see Section 5.2, “Operating Conditions” on
page 19 for limitations when operating the device with VPP = VPPH).
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