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參數(shù)資料
| 型號： | PF38F40L0YUQ0 |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 16M X 16 FLASH 1.8V PROM, PBGA88 |
| 封裝： | 8 X 11 MM, 1 MM HEIGHT, ROHS COMPLIANT, VFBGA-88 |
| 文件頁數(shù)： | 51/99頁 |
| 文件大?。?/td> | 1419K |
| 代理商： | PF38F40L0YUQ0 |
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Intel StrataFlash Wireless Memory (L18) with A/D-Multiplexed I/O
July 2006
Datasheet
Order Number: 313295-002US
55
Intel StrataFlash Wireless Memory (L18)
Read operation while performing Buffered EFP is not supported.
Notes:
1.
Word buffer boundaries in the array are determined by A[4:0] (0x00 through 0x1F). The alignment
start point is A[4:0] = 0x00.
2.
Some degradation in performance may occur if this limit is exceeded, but the internal algorithm
continues to work properly.
3.
If the internal address counter increments beyond the block's maximum address, addressing wraps
around to the beginning of the block.
4.
If the number of words is less than 32, remaining locations must be filled with 0xFFFF.
11.3.2
Buffered EFP Setup Phase
After receiving the Buffered EFP Setup and Confirm command sequence, Status
Register bit SR[7] (Ready) is cleared, indicating that the WSM is busy with Buffered EFP
algorithm startup. A delay before checking SR[7] is required to allow the WSM enough
time to perform all of its setups and checks (Block-Lock status, VPP level, etc.). If an
error is detected, SR[4] is set and Buffered EFP operation terminates. If the block was
found to be locked, SR[1] is also set. SR[3] is set if the error occurred due to an
incorrect VPP level.
Note:
Reading from the device after the Buffered EFP Setup and Confirm command sequence
outputs Status Register data. Do not issue the Read Status Register command; it will
be interpreted as data to be loaded into the buffer.
11.3.3
Buffered EFP Program/Verify Phase
After the Buffered EFP Setup Phase has completed, the host programming system must
check SR[7,0] to determine the availability of the write buffer for data streaming.
SR[7] cleared indicates the device is busy and the Buffered EFP program/verify phase
is activated. SR[0] indicates the write buffer is available.
Two basic sequences repeat in this phase: loading of the write buffer, followed by buffer
data programming to the array. For Buffered EFP, the count value for buffer loading is
always the maximum buffer size of 32 words. During the buffer-loading sequence, data
is stored to sequential buffer locations starting at address 0x00. Programming of the
buffer contents to the flash memory array starts as soon as the buffer is full. If the
number of words is less than 32, the remaining buffer locations must be filled with 0xFFFF.
Caution:
The buffer must be completely filled for programming to occur. Supplying an address outside of the
current block's range during a buffer-fill sequence causes the algorithm to exit immediately. Any
data previously loaded into the buffer during the fill cycle is not programmed into the array.
The starting address for data entry must be buffer size aligned, if not the Buffered EFP
algorithm will be aborted and the program fail (SR[4]) flag will be set.
Data words from the write buffer are directed to sequential memory locations in the
flash memory array; programming continues from where the previous buffer sequence
ended. The host programming system must poll SR[0] to determine when the buffer
program sequence completes. SR[0] cleared indicates that all buffer data has been
transferred to the flash array; SR[0] set indicates that the buffer is not available yet for
the next fill cycle. The host system may check full status for errors at any time, but it is
only necessary on a block basis after Buffered EFP exit.
The host programming system continues the Buffered EFP algorithm by providing the
next group of data words to be written to the buffer. Alternatively, it can terminate this
phase by changing the block address to one outside of the current block’s range.
The Program/Verify phase concludes when the programmer writes to a different block
address; data supplied must be 0xFFFF. Upon Program/Verify phase completion, the
device enters the Buffered EFP Exit phase.
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