- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄299768 > PF38F40L0YUQ0 (NUMONYX) 16M X 16 FLASH 1.8V PROM, PBGA88 PDF資料下載
參數(shù)資料
| 型號： | PF38F40L0YUQ0 |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 16M X 16 FLASH 1.8V PROM, PBGA88 |
| 封裝： | 8 X 11 MM, 1 MM HEIGHT, ROHS COMPLIANT, VFBGA-88 |
| 文件頁數(shù)： | 44/99頁 |
| 文件大小： | 1419K |
| 代理商： | PF38F40L0YUQ0 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁當前第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁
Intel StrataFlash Wireless Memory (L18) with A/D-Multiplexed I/O
July 2006
Datasheet
Order Number: 313295-002US
49
Intel StrataFlash Wireless Memory (L18)
NOTE:
Active: WAIT is asserted until data becomes valid, then de-asserts. WAIT is asserted during the initial
access (latency) and at the end of the burst cycle with OE# low.
10.3.4
Data Hold
For burst read operations, the Data Hold (DH) bit determines whether the data output
remains valid on AD[15:0] for one or two clock cycles. This period of time is called the
“
data cycle”. When DH is set, output data is held for two clocks (default). When DH is
cleared, output data is held for one clock (see Figure 18). The processor’s data setup
time and the flash memory’s clock-to-data output delay should be considered when
determining whether to hold output data for one or two clocks.
A method for determining the Data Hold configuration is shown below:
To set the device at one clock data hold for subsequent reads, the following condition
must be satisfied:
tCHQV (ns) + tDATA (ns) ≤ One CLK Period (ns)
tDATA = Data set up to Clock (defined by CPU)
For example, with a clock frequency of 54 MHz, the clock period is 18.5 ns. Assuming
tCHQV = 14ns and tDATA = 4ns. Applying these values to the formula above:
14 ns + 4 ns ≤ 18.5 ns
The equation is satisfied and data will be available at every clock period with data hold
setting at one clock.
If tCHQV (ns) + tDATA (ns) > One CLK Period (ns), data hold setting of 2 clock periods
must be used.
OE# = VIH
OE# = VIL
De-asserted
Active
Synchronous Array and
Non-array Reads
Active
All Asynchronous Read and
all Write
De-asserted
Table 18. WAIT Summary Table
CONDITION
WAIT
Figure 18. Data Hold Timing
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
CLK [C]
AD[15:0] [Q]
2 CLK
Data Hold
1 CLK
Data Hold
相關PDF資料 |
PDF描述 |
|---|---|
| PF50WIW2K-3.5VF-W6 | SINGLE COLOR LED, INCAND WHITE |
| PD50WO3K-28V-T | SINGLE COLOR LED, SUPER ORANGE |
| PD50WR3K-24V-W6 | SINGLE COLOR LED, ULTRA RED |
| PF50WAG6K-240VAC-W6 | SINGLE COLOR LED, AQUA GREEN |
| PF50WW1K-12V-W6 | SINGLE COLOR LED, COOL WHITE |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PF38F4470LLYBBEA | 制造商:Micron Technology Inc 功能描述:256LCR/256LCR/256SD SCSP 1.8 X16D LF - Trays |
| PF38F5050M0Y0CFA | 制造商:Micron Technology Inc 功能描述:512BA/64PS SCSP 1.8 LF MICRON - Trays |
| PF38F5050M0Y0CFB | 制造商:Micron Technology Inc 功能描述:512BA/64PS SCSP 1.8 LF MICRON - Tape and Reel |
| PF38F5050M0Y0CGA | 制造商:Micron Technology Inc 功能描述:512BA/64PS SCSP 1.8 LF MICRON - Trays |
| PF38F5060M0Y0BEA | 功能描述:IC FLASH 512MBIT 133MHZ 105SCSP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:3,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:32K (4K x 8) 速度:100kHz，400kHz 接口:I²C，2 線串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 125°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:8-SOIC 包裝:帶卷 (TR) 其它名稱:CAV24C32WE-GT3OSTR |
發(fā)布緊急采購，3分鐘左右您將得到回復。