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參數(shù)資料
| 型號(hào)： | PF38F40L0YUQ0 |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 16M X 16 FLASH 1.8V PROM, PBGA88 |
| 封裝： | 8 X 11 MM, 1 MM HEIGHT, ROHS COMPLIANT, VFBGA-88 |
| 文件頁(yè)數(shù)： | 41/99頁(yè) |
| 文件大?。?/td> | 1419K |
| 代理商： | PF38F40L0YUQ0 |
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Intel StrataFlash Wireless Memory (L18)
Intel StrataFlash Wireless Memory (L18) with A/D-Multiplexed I/O
Datasheet
July 2006
46
Order Number: 313295-002US
10.3.1
Read Mode
The Read Mode (RM) bit selects synchronous burst-mode or asynchronous read-mode
operation for the device. When the RM bit is set, asynchronous read mode is selected
(default). When RM is cleared, synchronous burst mode is selected.
10.3.2
Latency Count
The Latency Count bits, LC[2:0], tell the device how many clock cycles must elapse
from the rising edge of ADV# or from the first valid clock edge after ADV# is asserted
before the WAIT signal indicates valid data is present on the device data signals
AD[15:0]. The input clock frequency determines this value. Figure 16 shows the data
output latency from ADV#-asserted for different settings of LC[2:0]. The Latency Count
does not affect when data becomes available on the data signals. Valid data is driven
onto the data bus, with respect to a valid clock edge, as soon as possible after the
asynchronous access time is satisfied (or another word after it is sensed). In this way,
the data “flows-through” on the first access, with respect to an active clock edge. The
data continues to be available on the data bus until the latency period is over. The flow-
through behavior only applies to the first access of any bus cycle. All subsequent data
is driven on valid clock edges following the first access latency period.
Table 15. Read Configuration Register Description
Read Configuration Register (RCR)
Read
Mode
RES
Latency Count
WAIT
Polarity
Data
Hold
WAIT
Delay
Burst
Seq
CLK
Edge
RES
Burst
Wrap
Burst Length
RM
R
LC[2:0]
WP
DH
WD
BS
CE
R
BW
BL[2:0]
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit
Name
Description
15
Read Mode (RM)
0 = Synchronous burst-mode read
1 = Asynchronous read (default)
14
Reserved (R)
Reserved bits should be cleared (0)
13:11
Latency Count (LC[2:0])
010 =Code 2
011 =Code 3
100 =Code 4
101 =Code 5
110 =Code 6
111 =Code 7(default)
(Other bit settings are reserved)
10
Wait Polarity (WP)
0 =WAIT signal is active low
1 =WAIT signal is active high (default)
9
Data Hold (DH)
0 =Data held for a 1-clock data cycle
1 =Data held for a 2-clock data cycle (default)
8
Wait Delay (WD)
0 =WAIT de-asserted with valid data
1 =WAIT de-asserted one data cycle before valid data (default)
7
Burst Sequence (BS)
0 =Reserved
1 =Linear (default)
6
Clock Edge (CE)
0 = Falling edge
1 = Rising edge (default)
5:4
Reserved (R)
Reserved bits should be cleared (0)
3Burst Wrap (BW)
0 =Wrap; Burst accesses wrap within burst length set by BL[2:0]
1 =No Wrap; Burst accesses do not wrap within burst length (default)
2:0
Burst Length (BL[2:0])
001 =4-word burst
010 =8-word burst
011 =16-word burst
111 =Continuous-word burst (default)
(Other bit settings are reserved)
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