參數(shù)資料
型號： PDI1394L11
廠商： NXP Semiconductors N.V.
英文描述： 1394 AV Link Layer Controller(AV（音頻/視頻）鏈接層控制器)
中文描述： 1394影音鏈路層控制器（視聽（音頻/視頻）鏈接層控制器）
文件頁數(shù)： 9/46頁
文件大?。?/td> 294K
代理商： PDI1394L11
Philips Semiconductors
Product specification
PDI1394L11
1394 AV link layer controller
1997 Oct 21
9
12.3.2
To write to an internal register the host interface must collect the 4
byte values into a 32 bit value and then write the result to the target
register in a single clock tick. This requires a register to hold the 32
bit value being compiled until it is ready to be written to the actual
target register. This temporary register inside the host interface is
called the
write shadow register
. During all write cycles address
lines HIF A0 and HIF A1 are used to select which of the 4 bytes of
the
write shadow register
is to be written with the value on the
CPU data bus. Only one byte can be written in a single write access
cycle.
Write accesses
This solution requires a control line to direct the host interface to
copy the
write shadow register
to the actual destination register
when ready, as well as the internal address of that register. The
destination register address is connected to input address lines
HIF A2..HIF A7, and the update control line to input address line
HIF A8. To let the host interface make the internal transfer the target
address must be presented on HIF A2..HIF A7 and HIF A8 must be
raised while executing a write access. The current value on the CPU
data bus will be stored in the
write shadow register
at the selected
byte (HIF A0, HIF A1) and the result will be copied into the specified
destination register.
UPDATE/COPY CONTROL
HIF A8
HIF A2..7
HIF A0..1
CPU
W
8
32
32
REGISTERS
TR
Q
Q
MUX
MUX
SV00804
NOTES:
1. It is not required to write all 4 bytes of a register: those bytes that are either reserved (undefined) or don’t care do not have to be written in
which case they will be assigned the value that was left in the corresponding byte of the
write shadow register
from a previous write
access. For example, to acknowledge an interrupt for the isochronous receiver (external address 0x04C), a single byte write to location
0x100+(0x4C)+3 = 0x14F is sufficient. The value 256 represents setting HIF A8=1. The host interface cannot directly access the FIFOs, but
instead reads from/writes into a transfer register (shown as TR in the Figures above). Data is moved between FIFO and TR by internal logic
as soon as possible without CPU intervention.
2. The update control line does not necessarily have to be connected to the CPU address line HIF A8. This input could also be controlled by
other means, for example a combinatorial circuit that activates the update control line whenever a write access is done for byte 3. This
makes the internal updating automatic for quadlet writing.
3. Writing the bytes of the read shadow register can be done in any order and as often as needed (new writes simply overwrite the old value).
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PDI1394L11BA 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 AV link layer controller
PDI1394L11BA-S 制造商:未知廠家 制造商全稱:未知廠家 功能描述:IEEE 1394 (Firewire) Bus Interface/Controller
PDI1394L21 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 full duplex AV link layer controller
PDI1394L21BE 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 full duplex AV link layer controller
PDI1394L21BP 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 full duplex AV link layer controller
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