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參數(shù)資料
| 型號： | PDI1394L11 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 1394 AV Link Layer Controller(AV（音頻/視頻）鏈接層控制器) |
| 中文描述： | 1394影音鏈路層控制器（視聽（音頻/視頻）鏈接層控制器） |
| 文件頁數(shù)： | 5/46頁 |
| 文件大?。?/td> | 294K |
| 代理商： | PDI1394L11 |
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Philips Semiconductors
Product specification
PDI1394L11
1394 AV link layer controller
1997 Oct 21
5
9.2
AV Interface
PIN No.
77, 76, 75, 74,
71, 70, 69, 68
58
57
PIN SYMBOL
I/O
NAME AND FUNCTION
AV D[7:0]
I/O
Audio/Video Data 7 (MSB) through 0. Byte-wide interface to the AV layer.
AVCLK
AVSYNC
I
External application clock. Rising edge active.
Start of packet indicator; should only be used when AVVALID is active.
Frame sync input. Used for Digital Video (DV). The signal is time stamped and transmitted in
the SYT field of ITXHQ2.
Frame sync output. Signal is derived from SYT field of IRXHQ2.
End of application packet indication from data source. Required only if input packet is not
multiple of 4 bytes. It can be tied LOW for data packets that are 4*N in size.
Indicates data on AV D [7:0] is valid
CRC error, indicates bus packet containing AV D [7:0] had a CRC error, the current AV packet
is unreliable.
Sequence Error. Indicates at least one source packet was lost before the current AV D [7:0]
I/O
59
AVFSYNCIN
I
60
AVFSYNCOUT
O
56
AVENDPCK
I
61
AVVALID
I/O
53
AVERR0
O
52
AVERR1
O
9.3
Phy Interface
PIN No.
PIN SYMBOL
I/O
NAME AND FUNCTION
34, 35, 36, 37,
40, 41, 42, 43
PHY D[0:7]
I/O
Data 0 (MSB) through 7 (NOTE: To preserve compatibility to the specified Link-Phy interface
of the IEEE 1394–1995 standard, Annex J, bit 0 is the most significant bit). Data is expected
on AV D[0:1] for 100Mb/s, AV D[0:3] for 200Mb/s, and AV D[0:7] for 400Mb/s. See IEEE
1394–1995 standard, Annex J for more information.
Control Lines between Link and Phy. See 1394 Specification for more information.
Isolation barrier. This terminal is asserted (LOW) when an isolation barrier is present. See
IEEE 1394–1995 standard, Annex J for more information (used to request arbitration or
read/write PHY registers).
Link Request. Bus request to access the PHY. See IEEE 1394–1995 standard, Annex J for
more information.
System clock. 49.152MHz input from the PHY (the PHY-LINK interface operates at this
frequency).
46, 47
PHY CTL[0:1]
I/O
48
ISO_N
I
54
LREQ
O
55
SCLK
I
9.4
Other Pins
PIN No.
PIN SYMBOL
I/O
NAME AND FUNCTION
65, 66, 67
RESERVED
NA
These pins are reserved for factory testing. For normal operation they should be connected to
ground.
These are test mode pins and should not be connected or terminated.
Provides the capability to supply an external cycle timer signal for the beginning of 1394 bus
cycles.
Reproduces the 8kHz cycle clock of the cycle master.
Auxiliary clock, value is SCLK/2 (usually 24.576 MHz)
51, 62, 80
N/C
NA
30
CYCLEIN
I
33
11
CYCLEOUT
CLK 25
O
O
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| PDI1394L21 | Full Duplex AV Link Layer Ccontroller(全雙工AV鏈接層控制器) |
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| PDI1394P21 | 3-port Physical Layer Interface(三端口物理層接口) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PDI1394L11BA | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 AV link layer controller |
| PDI1394L11BA-S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:IEEE 1394 (Firewire) Bus Interface/Controller |
| PDI1394L21 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 full duplex AV link layer controller |
| PDI1394L21BE | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 full duplex AV link layer controller |
| PDI1394L21BP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 full duplex AV link layer controller |
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