參數(shù)資料
型號(hào)： PDI1394L11
廠商： NXP Semiconductors N.V.
英文描述： 1394 AV Link Layer Controller(AV（音頻/視頻）鏈接層控制器)
中文描述： 1394影音鏈路層控制器（視聽(tīng)（音頻/視頻）鏈接層控制器）
文件頁(yè)數(shù)： 11/46頁(yè)
文件大?。?/td> 294K
代理商： PDI1394L11
Philips Semiconductors
Product specification
PDI1394L11
1394 AV link layer controller
1997 Oct 21
11
SV00686
T
AS
HIF CS_N
HIF RD_N
HIF WR_N
HIF A0..HIF A7
HIF D0..HIF D7
T
AS
T
ACC
T
ACC
RSR
O
RSR
n
RSR
n
HIF A8
Figure 2. Read cycle signal timing (2 independent read cycles)
SV00687
T
AS
HIF CS_N
HIF RD_N
HIF WR_N
HIF A0..HIF A8
HIF D0..HIF D7
T
AS
<WRITE DATA>
<WRITE DATA>
<VALID ADDRESS>
<VALID ADDRESS>
Figure 3. Write cycle signal timing (2 independent write cycles)
12.4
The PDI1394L11 provides an interface to asynchronous data
packets through the registers in the host interface. The format of the
asynchronous packets is specified in the following sections.
The Asynchronous Packet Interface
12.4.1
Upon reception of a packet, the packet data is stored in the
appropriate receive FIFO, either the Request or Response FIFO.
The location of the packet is indicated by either the RREQQQAV or
RRSPQAV status bit being set in the Asynchronous Interrupt
Acknowledge (ASYINTACK) register. The packet is transferred out
of the FIFO by successive reads of the Asynchronous Receive
Request (RREQ) or Asynchronous Receive Response (RRSP)
register. The end of the packet (the last quadlet) is indicated by
either the RREQQLASTQ or RRSPQLASTQ bit set in ASYINTACK.
Attempting to read the FIFO when either RREQQQAV bit or
RRSPQQAV bit is set to 0 (in the Asynchronous RX/TX interrupt
acknowledge (ASYINTACK) register) will result in a queue read
error.
Reading an Asynchronous Packet
12.4.2
An asynchronous packet intended for transmission is first stored in
the appropriate Transmitter FIFO. Once writing to the FIFO is
complete, the link layer controller arbitrates for the bus to transmit
the packet.
Writing an Asynchronous Packet
To generate an asynchronous packet, the first and next to last
quadlets of the packet must be written to the Asynchronous
Transmit Request Next (TX_RQ_NEXT) register, for request type
packets, or the Asynchronous Transmit Response Next
(TX_RP_NEXT) register, for response type packets. The last
quadlet of the packet is written to the Asynchronous Transmit
Request Last (TX_RQ_LAST) register, for request type packets, or
the Asynchronous Transmit Response Last (TX_RP_LAST)
register, for response type packets. After writing the last quadlet,
the packet is automatically queued by the AVlink layer controller for
transmission over the bus.
相關(guān)PDF資料
PDF描述
PDI1394L21 Full Duplex AV Link Layer Ccontroller(全雙工AV鏈接層控制器)
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PDI1394P21 3-port Physical Layer Interface(三端口物理層接口)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PDI1394L11BA 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:1394 AV link layer controller
PDI1394L11BA-S 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:IEEE 1394 (Firewire) Bus Interface/Controller
PDI1394L21 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:1394 full duplex AV link layer controller
PDI1394L21BE 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:1394 full duplex AV link layer controller
PDI1394L21BP 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:1394 full duplex AV link layer controller
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