參數(shù)資料
型號(hào)： PDI1394L11
廠商： NXP Semiconductors N.V.
英文描述： 1394 AV Link Layer Controller(AV（音頻/視頻）鏈接層控制器)
中文描述： 1394影音鏈路層控制器（視聽（音頻/視頻）鏈接層控制器）
文件頁數(shù)： 32/46頁
文件大?。?/td> 294K
代理商： PDI1394L11
Philips Semiconductors
Product specification
PDI1394L11
1394 AV link layer controller
1997 Oct 21
32
Bit 3..2:
R/W
PM: packing mode:
00 = variable sized bus packets, most generic mode.
01 = fixed size bus packets.
10 = MPEG–2 packing mode.
11 = No data, just CIP headers are transmitted.
EN_FS:enable generation/insertion of SYT stamps (Time Stamps) in CIP header.
Reset Isochronous Transmitter: causes transmitter to be reset when ‘1’. In order for synchronous reset of ITX to
work properly, the application must supply an AVCLK and ensure that the reset bit is kept (programmed) HIGH for
at least the duration of one AVCLK period. Failure to do so may cause the application interface of this module
to be improperly reset (or not reset at all).
Bit 1:
Bit 0:
R/W
R/W
13.2.2
The AV Transmit Packing Control register holds the specification for the packing scheme used on the AV data stream. This information is
included in Common Isochronous Packet (CIP) header quadlet 1.
Common Isochronous Transmit Packet Header Quadlet 1 (ITXHQ1) – Base Address: 0x024
29 28 272625 24 23 22 212019 18 1716 15 1413 12 11 10 9 8 7 6 5 4 3 2 1 0
S
QPC
FN
DBS
SV00280
3130
Reset Value 0x00000000
Bit 10:
Bit 11..13:
R/W
R/W
SPH: Indicates that a 25-bit CYCTM based time stamp has to be inserted before each application packet.
QPC: Number of dummy quadlets to append to each source packet before it is divided into data blocks of the
specified size. The value QPC must be less than DBS and less than 2
FN
.
FN: (Fraction Number) The encoding for the number of data blocks into which each source packet shall be divided
(00 = 1, 01 = 2, 10 = 4, 11 = 8).
DBS: Size of the data blocks from which AV payload is constructed. The value 0 represents a length of 256 quadlets.
Bit 14..15:
R/W
Bit 16..23:
R/W
13.2.3
The contents of this register are copied to the second quadlet of the CIP header and transmitted with each isochronous packet.
Common Isochronous Transmit Packet Header Quadlet 2 (ITXHQ2) – Base Address: 0x028
29 28 272625 24 23 22 212019 18 1716 15 1413 12 11 10 9 8 7 6 5 4 3 2 1 0
FMT
FDF
SV00281
3130
SYT
Reset Value 0x00000000
Bit 29..24:
Bit 23..0:
R/W
R/W
FMT: Value to be inserted in the FMT field in the AV header.
FDF/SYT: Value to be inserted in the FDF field. When the EN_FS bit in the Transmit Control and Status Register
(ITXPKCTL) is set (=1), the lower 16 bits of this register are replaced by an SYT stamp if a rising edge on
AVFSYNCIN has been detected or all ‘1’s if no such edge was detected since the previous packet. The upper 8 bits
of the register are sent as they appear in the FDF register. When the EN_FS bit in the Transmit Control and Status
Register is unset (=0), the full 24 bits can be set to any application specified value.
相關(guān)PDF資料
PDF描述
PDI1394L21 Full Duplex AV Link Layer Ccontroller(全雙工AV鏈接層控制器)
PDI1394L41 Content Protection AV Link Layer(內(nèi)容可保護(hù)的AV鏈接層控制器)
PDI1394P21 3-port Physical Layer Interface(三端口物理層接口)
PDI1394P22 3-port Physical Layer Interface(三端口物理層接口)
PDI1394P24 2-port 400 Mbps physical layer interface(2端口 400 Mbps物理層接口)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PDI1394L11BA 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 AV link layer controller
PDI1394L11BA-S 制造商:未知廠家 制造商全稱:未知廠家 功能描述:IEEE 1394 (Firewire) Bus Interface/Controller
PDI1394L21 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 full duplex AV link layer controller
PDI1394L21BE 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 full duplex AV link layer controller
PDI1394L21BP 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 full duplex AV link layer controller
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*