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Chapter 20 Serial Peripheral Interface (S12SPIV5)
MC9S12XE-Family Reference Manual Rev. 1.07
Freescale Semiconductor
775
20.3.2.2
SPI Control Register 2 (SPICR2)
Read: Anytime
Write: Anytime; writes to the reserved bits have no effect
Table 20-2. SS Input / Output Selection
MODFEN
SSOE
Master Mode
Slave Mode
0
SS not used by SPI
SS input
0
1
SS not used by SPI
SS input
1
0
SS input with MODF feature
SS input
1
1
SS is slave select output
SS input
Module Base +0x0001
7
0
6
5
0
4
3
2
0
1
0
R
W
XFRW
MODFEN
BIDIROE
SPISWAI
SPC0
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 20-4. SPI Control Register 2 (SPICR2)
Table 20-3. SPICR2 Field Descriptions
Field
Description
6
XFRW
Transfer Width —
This bit is used for selecting the data transfer width. If 8-bit transfer width is selected, SPIDRL
becomes the dedicated data register and SPIDRH is unused. If 16-bit transfer width is selected, SPIDRH and
SPIDRL form a 16-bit data register. Please refer to
Section 20.3.2.4, “SPI Status Register (SPISR)
for
information about transmit/receive data handling and the interrupt flag clearing mechanism. In master mode, a
change of this bit will abort a transmission in progress and force the SPI system into idle state.
0 8-bit Transfer Width (n = 8)
1
1 16-bit Transfer Width (n = 16)
1
4
MODFEN
Mode Fault Enable Bit
— This bit allows the MODF failure to be detected. If the SPI is in master mode and
MODFEN is cleared, then the SS port pin is not used by the SPI. In slave mode, the SS is available only as an
input regardless of the value of MODFEN. For an overview on the impact of the MODFEN bit on the SS port pin
configuration, refer to
Table 20-2
. In master mode, a change of this bit will abort a transmission in progress and
force the SPI system into idle state.
0 SS port pin is not used by the SPI.
1 SS port pin with MODF feature.
3
BIDIROE
Output Enable in the Bidirectional Mode of Operation
— This bit controls the MOSI and MISO output buffer
of the SPI, when in bidirectional mode of operation (SPC0 is set). In master mode, this bit controls the output
buffer of the MOSI port, in slave mode it controls the output buffer of the MISO port. In master mode, with SPC0
set, a change of this bit will abort a transmission in progress and force the SPI into idle state.
0 Output buffer disabled.
1 Output buffer enabled.