參數(shù)資料
型號: P89CV51RC2FA,512
廠商: NXP Semiconductors
文件頁數(shù): 8/76頁
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 32K 44-PLCC
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 26
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: EBI/EMI,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
其它名稱: 568-4254-5
935284108512
P89CV51RC2FA
P89CV51RB2_RC2_RD2_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 25 August 2009
16 of 76
NXP Semiconductors
P89CV51RB2/RC2/RD2
80C51 with 1 kB RAM, SPI
6.2.3 Reset
At initial power-up, the port pins will be in a random state until the oscillator has started
and the internal reset algorithm has weakly pulled all pins HIGH. Powering up the device
without a valid reset could cause the MCU to start executing instructions from an
indeterminate location. Such undened states may inadvertently corrupt the code in the
ash. A system reset will not affect the on-chip RAM while the device is running, however,
the contents of the on-chip RAM during power-up are indeterminate.
When power is applied to the device, the RST pin must be held HIGH long enough for the
oscillator to start-up (usually several milliseconds for a low frequency crystal), in addition
to two machine cycles for a valid power-on reset. An example of a method to extend the
RST signal is to implement an RC circuit by connecting the RST pin to VDD through a
10
F capacitor and to V
SS through an 8.2 k resistor as shown in Figure 6.
During initial power-up the POF ag in the PCON register is set to indicate an initial
power-up condition. The POF ag will remain active until cleared by software.
Fig 5.
Dual data pointer organization
Table 8.
AUXR1 - Auxiliary function register 1 (address A2H) bit allocation
Not bit addressable; reset value 00H.
Bit
7
6
5
4
3
2
1
0
Symbol
-
ENBOOT
-
GF2
0
-
DPS
Table 9.
AUXR1 - Auxiliary function register 1 (address A2H) bit description
Bit
Symbol
Description
7, 6, 4
-
Reserved for future use. Should be set to 0 by user programs.
5
ENBOOT
Enable BOOTROM
3
GF2
General purpose user-dened Flag.
2
0
This bit contains a hard-wired 0. Allows toggling of the DPS bit by
incrementing AUXR1, without interfering with other bits in the register.
1
-
Reserved for future use. Should be set to 0 by user programs.
0
DPS
Data Pointer Select. Chooses one of two data pointers for use by the
program. See text for details.
DPL
82H
DPS = 0
→ DPTR0
DPS = 1
→ DPTR1
external data memory
DPS
002aaa518
DPH
83H
DPTR0
DPTR1
AUXR1 / bit0
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