參數(shù)資料
型號: P89CV51RC2FA,512
廠商: NXP Semiconductors
文件頁數(shù): 25/76頁
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 32K 44-PLCC
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 26
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: EBI/EMI,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
其它名稱: 568-4254-5
935284108512
P89CV51RC2FA
P89CV51RB2_RC2_RD2_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 25 August 2009
31 of 76
NXP Semiconductors
P89CV51RB2/RC2/RD2
80C51 with 1 kB RAM, SPI
6.5.1 Capture mode
In the Capture mode there are two options which are selected by bit EXEN2 in T2CON. If
EXEN2 = 0 Timer 2 is a 16-bit timer or counter (as selected by C/T2 in T2CON) which
upon overowing sets bit TF2, the Timer 2 overow bit. The Capture mode is illustrated in
This bit can be used to generate an interrupt (by enabling the Timer 2 interrupt bit ET2 in
the IE register). If EXEN2 = 1, Timer 2 operates as described above, but with the added
feature that a 1-to-0 transition at external input T2EX causes the current value in the
Timer 2 registers, TL2 and TH2, to be captured into registers RCAP2L and RCAP2H,
respectively.
In addition, the transition at T2EX causes bit EXF2 in T2CON to be set, and EXF2 like
TF2 can generate an interrupt (which vectors to the same location as Timer 2 overow
interrupt). The Timer 2 interrupt service routine can interrogate TF2 and EXF2 to
determine which event caused the interrupt.
4
TCLK
Transmit clock ag. When set, causes the UART to use Timer 2 overow
pulses for its transmit clock in modes 1 and 3. TCLK = 0 causes Timer 1
overows to be used for the transmit clock.
3
EXEN2
Timer 2 external enable ag. When set, allows a capture or reload to occur
as a result of a negative transition on T2EX if Timer 2 is not being used to
clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
2
TR2
Start/stop control for Timer 2. A logic 1 enables the timer to run.
1C/T2
Timer or counter select. (Timer 2)
0 = internal timer (fosc /6)
1 = external event counter (falling edge triggered; external clock’s
maximum rate = fosc / 12)
0
CP/RL2
Capture/Reload ag. When set, captures will occur on negative transitions
at T2EX if EXEN2 = 1. When cleared, auto-reloads will occur either with
Timer 2 overows or negative transitions at T2EX when EXEN2 = 1. When
either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to
auto-reload on Timer 2 overow.
Table 21.
T2MOD - Timer 2 mode control register (address C9H) bit allocation
Not bit addressable; reset value: XX00 0000B.
Bit
7
6
5
4
3
2
1
0
Symbol
-
T2OE
DCEN
Table 22.
T2MOD - Timer 2 mode control register (address C9H) bit description
Bit
Symbol
Description
7 to 2
-
Reserved for future use. Should be set to 0 by user programs.
1
T2OE
Timer 2 Output Enable bit. Used in programmable Clock-out mode only.
0
DCEN
Down Count Enable bit. When set, this allows Timer 2 to be congured as
an up/down counter.
Table 20.
T2CON - Timer/Counter 2 control register (address C8H) bit description …continued
Bit
Symbol
Description
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