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參數(shù)資料
| 型號(hào)： | P89CV51RC2FA,512 |
| 廠商： | NXP Semiconductors |
| 文件頁(yè)數(shù)： | 52/76頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC 80C51 MCU FLASH 32K 44-PLCC |
| 產(chǎn)品培訓(xùn)模塊： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs |
| 標(biāo)準(zhǔn)包裝： | 26 |
| 系列： | 89C |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | EBI/EMI，SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲(chǔ)器容量： | 32KB（32K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 包裝： | 管件 |
| 其它名稱： | 568-4254-5 935284108512 P89CV51RC2FA |
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P89CV51RB2_RC2_RD2_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 25 August 2009
56 of 76
NXP Semiconductors
P89CV51RB2/RC2/RD2
80C51 with 1 kB RAM, SPI
6.12 Power-saving modes
The device provides two power-saving modes of operation for applications where power
consumption is critical. The two modes are Idle and Power-down; see Table 48.
6.12.1 Idle mode
Idle mode is entered by setting the IDL bit in the PCON register. In Idle mode, the program
counter is stopped. The system clock continues to run and all interrupts and peripherals
remain active. The on-chip RAM and the special function registers hold their data during
this mode.
The device exits Idle mode through either a system interrupt or a hardware reset. When
exiting Idle mode via system interrupt, the start of the interrupt clears the IDL bit and exits
Idle mode. After exiting the Interrupt Service Routine (ISR), the interrupted program
resumes execution at the instruction immediately following the instruction which invoked
the Idle mode. A hardware reset starts the device similar to a power-on reset.
6.12.2 Power-down mode
The Power-down mode is entered by setting the PD bit in the PCON register. In the
Power-down mode, the clock is stopped and external interrupts are active for
level-sensitive interrupts only. SRAM contents are retained during power-down, the
minimum VDD level is 4.5 V.
The device exits Power-down mode through either an enabled external level-sensitive
interrupt or a hardware reset. The start of the interrupt clears the PD bit and exits
power-down. Holding an external interrupt pin LOW restarts the oscillator, the signal must
hold LOW at least 1024 clock cycles before bringing back HIGH to complete the exit.
When the interrupt signal is restored to logic VIH, the interrupt service routine program
execution resumes at the instruction immediately following the instruction which invoked
Power-down mode. A hardware reset starts the device similar to a power-on reset.
To exit properly out of power-down, the reset or external interrupt should not be executed
before the VDD line is restored to its normal operating voltage. Be sure to hold VDD voltage
long enough at its normal operating level for the oscillator to restart and stabilize (normally
less than 10 ms).
Table 48.
Power-saving modes
Mode
Initiated by
State of MCU
Exited by
Idle
Software (Set IDL bit
in PCON)
MOV PCON, #01H
CLK is running. Interrupts, serial
port and timers/counters are
active. Program counter is
stopped. ALE and PSEN signals
at a HIGH-state during Idle. All
registers remain unchanged.
Enabled interrupt or hardware reset. Start of
interrupt clears IDL bit and exits Idle mode, after
the ISR RETI instruction, program resumes
execution beginning at the instruction following the
one that invoked Idle mode. A hardware reset
restarts the device similar to a power-on reset.
Power-down
Software (Set PD bit
in PCON)
MOV PCON, #02H
CLK is stopped. On-chip SRAM
and SFR data is maintained.
ALE and PSEN signals at a
LOW-state during power-down.
External interrupts are only
active for level-sensitive
interrupts, if enabled.
Enabled external level-sensitive interrupt or
hardware reset. Start of interrupt clears PD bit and
exits Power-down mode, after the ISR RETI
instruction program resumes execution beginning
at the instruction following the one that invoked
Power-down mode. A hardware reset restarts the
device similar to a power-on reset.
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| P89CV51RC2FBC | 功能描述:8位微控制器 -MCU 80C51 32K FL / 512 R RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| P89CV51RC2FBC,557 | 功能描述:8位微控制器 -MCU 80C51 32K FL / 512 R RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| P89CV51RD2 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit 80C51 5 V low power 64 kB flash microcontroller with 1 kB RAM, SPI, 6-clock CPU with 6/12-clock peripherals |
| P89CV51RD2FA | 制造商: 功能描述: 制造商:undefined 功能描述: |
| P89CV51RD2FA,512 | 功能描述:8位微控制器 -MCU 64K/1K FL 12 CLK ISP/IAP IND RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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