參數(shù)資料
型號: P89CV51RC2FA,512
廠商: NXP Semiconductors
文件頁數(shù): 5/76頁
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 32K 44-PLCC
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 26
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: EBI/EMI,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
其它名稱: 568-4254-5
935284108512
P89CV51RC2FA
P89CV51RB2_RC2_RD2_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 25 August 2009
13 of 76
NXP Semiconductors
P89CV51RB2/RC2/RD2
80C51 with 1 kB RAM, SPI
6.2 Memory organization
The various P89CV51RB2/RC2/RD2 memory spaces are as follows:
DATA
128 B of internal data memory space (00H:7FH) accessed via direct or indirect
addressing, using instructions other than MOVX and MOVC. All or part of the stack
may be in this area.
IDATA
Indirect Data. 256 B of internal data memory space (00H:FFH) accessed via indirect
addressing using instructions other than MOVX and MOVC. All or part of the stack
may be in this area. This area includes the DATA area and the 128 B immediately
above it.
SFR
Special Function Registers. Selected CPU registers and peripheral control and status
registers, accessible only via direct addressing.
XDATA
‘External’ Data or auxiliary RAM. Duplicates the classic 80C51 64 kB memory space
addressed via the MOVX instruction using the DPTR, R0, or R1. The
P89CV51RB2/RC2/RD2 have 768 B of on-chip XDATA memory.
CODE
64 kB of code memory space, accessed as part of program execution and via the
MOVC instruction. The P89CV51RB2/RC2/RD2 have 16/32/64 kB of on-chip code
memory.
6.2.1 Expanded data RAM addressing
The P89CV51RB2/RC2/RD2 have 1 kB of data RAM; see Figure 4.
To access the expanded RAM (XRAM), the EXTRAM bit must be set and MOVX
instructions must be used. The expanded memory is physically located on the chip and
logically occupies the rst bytes of external memory (addresses 000H to 2FFH).
When EXTRAM = 0, the expanded RAM is indirectly addressed using the MOVX
instruction in combination with any of the registers R0, R1 of the selected bank or DPTR.
Accessing the expanded RAM does not affect ports P0, P3[6] (WR), P3[7] (RD), or P2.
With EXTRAM = 0, the expanded RAM can be accessed as in the following example.
Expanded RAM access (indirect addressing only):
MOVX @DPTR, A; DPTR contains 0A0H
Table 5.
AUXR - Auxiliary function register (address 8EH) bit allocation
Not bit addressable; reset value 00H.
Bit
7
6
5
4
3
2
1
0
Symbol
-
EXTRAM
AO
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P89CV51RD2FA 制造商: 功能描述: 制造商:undefined 功能描述:
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