參數(shù)資料
型號： NS7520B-1-I55
廠商： Digi International
文件頁數(shù)： 66/68頁
文件大小： 0K
描述： IC ARM MICROPROCESSOR 177BGA
標準包裝： 160
系列： NET+ARM®
應用： 網(wǎng)絡處理器
核心處理器： ARM7
程序存儲器類型： 外部程序存儲器
RAM 容量： 外部
接口： EBI/EMI，以太網(wǎng)，DMA，SPI，UART
輸入/輸出數(shù)： 16
電源電壓： 1.4 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 177-LFBGA
包裝： 托盤
供應商設備封裝： 177-BGA（13x13）
Operating freque ncy
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Operating frequency
The NS7520 is available in grades operating at three maximum operating frequencies: 36 MHz,
46 MHz, and 55 MHz. The operating frequency is set during bootstrap initialization, using pins
A[8:0]. These address pins load the PLL Settings register on powerup reset. A[8:7] determines IS
(charge pump current); A[6:5] determines FS (output divider), and A[4:0] defines ND (PLL
multiplier). Each bit in A[8:0] can be set individually. See the discussion of the PLL Settings register
in the NS7520 Hardware Reference for more information.
Serial ports
Bus interface
Two fully independent serial ports (UART, SPI)
Digital phase lock loop (DPLL) for receive clock
extractions
32-byte transmit/receive FIFOs
Internal programmable bit-rate generators
Bit rates 75–230400 in 16X mode
Bit rates 1200 bps–4 Mbps in 1X mode
Flexible baud rate generator, external clock for
synchronous operation
Receive-side character and buffer gap timers
Four receive-side data match detectors
Five independent programmable chip selects
with 256 Mb addressing per chip select
Chip select support for SRAM, FP/EDO DRAM,
SDRAM, Flash, and EEPROM without external
glue
8-, 16-, and 32-bit peripheral support
External address decoding and cycle termination
Dynamic bus sizing
Internal DRAM/SDRAM controller with address
multiplexer and programmable refresh frequency
Internal refresh controller (CAS before RAS)
Burst-mode support
0–63 wait states per chip select
Address pins that configurem chip operating
Power and Operating Voltages
500 mW maximum at 55 MHz (all outputs
switching)
418 mW maximum at 46 MHz (all outputs
switching)
291 mW maximum at 36 MHz (all outputs
switching)
3.3 V — I/O
1.5 V — Core
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