SRAM WE write WE* controlled write (wait = 2) Notes: 1 At least one null period occurs between " />
參數(shù)資料
型號: NS7520B-1-I55
廠商: Digi International
文件頁數(shù): 37/68頁
文件大?。?/td> 0K
描述: IC ARM MICROPROCESSOR 177BGA
標準包裝: 160
系列: NET+ARM®
應用: 網(wǎng)絡處理器
核心處理器: ARM7
程序存儲器類型: 外部程序存儲器
RAM 容量: 外部
接口: EBI/EMI,以太網(wǎng),DMA,SPI,UART
輸入/輸出數(shù): 16
電源電壓: 1.4 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 177-LFBGA
包裝: 托盤
供應商設備封裝: 177-BGA(13x13)
SRAM timing
38
NS 75 20 Da ta shee t
03 /2 00 6
SRAM WE write
WE* controlled write (wait = 2)
Notes:
1
At least one null period occurs between memory transfers. More null periods can occur if the
next transfer is DMA. Thirteen clock pulses are required for DMA context switching.
2
Port size determines which byte enable signals are active:
8-bit port = BE3*
16-bit port = BE[3:0]
32-bit port = BE[3:0]
3
The TW cycles are present when the WAIT field is set to 2 or more.
4
The TA* and TEA*/LAST signals are for reference only.
T1
TW
T2
Note-1
T1
12
19
29
13
9
27
36
6
31
30
15
14
Note-2
BCLK
TA* (Note-4)
TEA*/LAST (note-4)
TA* (input)
A[27:0]
BE[3:0]*
CS[4:0]*
write D[31:0]
Async WE*
CS0WE*
RW*
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