![](http://datasheet.mmic.net.cn/Digi-International/NS7520B-1-I55_datasheet_99197/NS7520B-1-I55_52.png)
FP D R AM timing
48
NS 93 60 Da ta shee t
03 /2 00 6
FP DRAM timing
BCLK max frequency: 55.296 MHz
Operating conditions:
FP DRAM timing parameters
Temperature:
-15.00 (min)
110.00 (max)
Voltage:
1.60 (min)
1.40 (max)
Output load:
25.0pf
Input drive:
CMOS buffer
Num
Description
Min
Max
Unit
36
BCLK high to BE* valid
15.5
ns
6
BCLK high to address valid
5
13.5
ns
9
BCLK high to data out valid
14
ns
13
BCLK high to data out high impedance
13
ns
10
Data in valid to BCLK high (setup)
5
ns
11
BCLK high to data in invalid (hold)
3
ns
14
TA* valid to BCLK high (setup)
5
ns
15
BCLK high to TA* invalid (hold)
3
ns
28
BCLK low to OE* valid
12.5
ns
29
BCLK low to WE* valid
13
ns
30
BCLK high to TA* valid
13.5
ns
31
BCLK high to TEA* valid
16
ns
37
BCLK high to PORTA2/AMUX valid
14
ns
35
BCLK high to muxed address valid
6
14.5
ns
43
BCLK low to CAS* valid
13
ns
27
BCLK low to RAS* valid
12
ns
12
BCLK high to RW* valid
13.5
ns