![](http://datasheet.mmic.net.cn/Digi-International/NS7520B-1-I55_datasheet_99197/NS7520B-1-I55_63.png)
Ex te rna l DM A tim i ng
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59
External DMA timing
BCLK max frequency: 55.296 MHz
Operating conditions:
External DMA timing parameters
Fly-by external DMA
Notes:
1
The memory signals are data[31:0], addr[27:0], BE[3:0], CS/RAS[4:0], CAS[3:0], RW, OE*. WE*,
and PORTC3/AMUX. The timing of these signals depends on how the memory is configured
(Sync SRAM, Async SRAM, FP DRAM, or SDRAM).
2
The DONE* signal works as an input only when the DMA channel is configured as fly-by write.
Temperature:
-15.00 (min)
110.00 (max)
Voltage:
1.60 (min)
1.40 (max)
Output load:
25.0pf
Input drive:
CMOS buffer
Num
Description
Min
Max
Unit
72
BCLK high to DACK* valid
14
ns
75
BCLK high to DONE* (output) valid
15
ns
70
DREQ* low to BCLK high (setup)
5
ns
71
BCLK high to DREQ* valid (hold)
0
ns
73
DONE* (input) valid BCLK high (setup)
5
ns
74
BLCK high to DONE* (input) valid (hold)
0
ns
T1
TW
T2
75
72
74
73
71
70
Note2
BCLK
Mem signals (Note-1)
DREQ*
DACK*
DONE* (output)
DONE* (input)