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| 型號： | NCN6001DTBR2 |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 4/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTERFACE SMART CARD 20TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 應(yīng)用： | 智能卡 |
| 接口： | 微控制器 |
| 電源電壓： | 2.75 V ~ 5.5 V |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 安裝類型： | 表面貼裝 |
| 其它名稱： | NCN6001DTBR2OSDKR |
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NCN6001
http://onsemi.com
12
Table 2. WRT_REG BITS DEFINITIONS AND FUNCTIONS
ADDRESS
PARAMETERS
CHIP
BANK
MOSI bits
[b3:b2]
MOSI bits
[b1:b0]
MOSI bits
[b7:b0]
1
b7
b6
b5
b4
b3
b2
b1
b0
CRD_CLK
CRD_VCC
CRD_DET
1
0
X
RST
0
Low
0
1
0
X
RST
0
1
0
1
1/1
1.8 V
1
0
X
RST
1
0
1
0
1/2
3.0 V
1
0
X
RST
1
1/4
5.0 V
1
0
1
0
NO
1
0
1
0
1
NC
1
0
1
0
1
0
Special
1
0
1
0
1
Normal
1
0
1
0
1
0
SLO_SLP
1
0
1
0
1
0
1
FST_SLP
1
RFU
2
1
0
RST
0
Low
0
2
1
0
RST
0
1
0
1
1/1
1.8 V
2
1
0
RST
1
0
1
0
1/2
3.0 V
2
1
0
RST
1
1/4
5.0 V
2
1
0
RST
CLK
I/O
C4
C8
Data to Sync. Card
2
1
0
1
0
NO
2
1
0
1
0
1
NC
2
1
0
1
0
1
0
Special
2
1
0
1
0
1
Normal
2
1
0
1
0
1
0
SLO_SLP
2
1
0
1
0
1
0
1
FST_SLP
2
1
RFU
11. Chip Bank 1 = Asynchronous cards, four slots addresses 1 to 4.
Chip Bank 2 = Asynchronous or synchronous card, single slot.
12.Address 101 and bits [b0 : b4] not documented in the table are reserved for future use.
Address 111 is reserved for future use.
Although using the %111XXXXX code is harmless from
a NCN6001 silicon standpoint, care must be observed to
avoid uncontrolled operation of the interface sharing the
same digital bus. When this code is presented on the digital
bus, the CRD_RST signal of any interface sharing the CS
signal, immediately reflects the digital content of the MOSI
bit b4 register. Similarly, the MISO register of the shared
interface is presented on the SPI port. Consequently, data
collision, at MISO level, and uncontrolled card operation are
likely to happen if the system uses a common Chip Select
line. It is strongly recommended to run a dedicated CS bit to
any external circuit intended to use the $111xxxxx code.
On the other hand, the CRD_RST signal will be forced to
Low when the internal register of the chip is programmed to
accommodate different hardware conditions (NO/NC,
Special/Normal, SLO_SLP/FST_SLP). Generally speaking,
such a configuration shall take place during the Power On
Reset to avoid CRD_RST activation.
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