參數(shù)資料
型號(hào)： NCN6001DTBR2
廠商： ON Semiconductor
文件頁(yè)數(shù)： 19/36頁(yè)
文件大?。?/td> 0K
描述： IC INTERFACE SMART CARD 20TSSOP
標(biāo)準(zhǔn)包裝： 1
應(yīng)用： 智能卡
接口： 微控制器
電源電壓： 2.75 V ~ 5.5 V
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 20-TSSOP
包裝： 標(biāo)準(zhǔn)包裝
安裝類(lèi)型： 表面貼裝
其它名稱(chēng)： NCN6001DTBR2OSDKR
NCN6001
http://onsemi.com
26
SMART CARD CLOCK DIVIDER
The main purpose of the builtin clock generator is
threefold:
1. Adapts the voltage level shifter to cope with the
different voltages that might exist between the
MPU and the Smart Card.
2. Provides a frequency division to adapt the Smart
Card operating frequency from the external clock
source.
3. Controls the clock state according to the smart
card specification.
In addition, the NCN6001 adjusts the signal coming from
the microprocessor to get the Duty Cycle window as defined
by the ISO78163 specification.
The byte content of the SPI port, B2 & B3, fulfills the
programming functions when CS is Low as depicted in
Figure 26 and Figure 25. The clock input stage (CLK_IN)
can handle a 20 MHz frequency maximum signal, the
divider being capable to provide a 1:4 ratio. Of course, the
ratio must be defined by the engineer to cope with the Smart
Card considered in a given application and, in any case, the
output clock [CRD_CLK] shall be limited to 20 MHz
maximum. In order to minimize the dI/dt and dV/dV
developed in the CRD_CLK line, the output stage includes
a special function to adapt the slope of the clock signal for
different applications. This function is programmed by the
MOSI register (Table 2: WRT_REG Bits Definitions and
Functions) whatever be the clock division.
In order to avoid any duty cycle out of the smart card
ISO78163 specification, the divider is synchronized by the
last flip flop, thus yielding a constant 50% duty cycle,
whatever be the divider ratio (Figure 25). Consequently, the
output CRD_CLK frequency division can be delayed by
four CLK_IN pulses and the microcontroller software must
take this delay into account prior to launch a new data
transaction. On the other hand, the output signal Duty Cycle
cannot be guaranteed 50% if the division ratio is 1 and if the
input Duty Cycle signal is not within the 46–56% range.
The input signals CLK_IN and MOSI/b3 are
automatically routed to the level shifter and control block
according to the mode of operation.
CRD_CLK
CLOCK_IN
CLOCK : 2
CLOCK : 4
B2
B3
Clock is updated upon
These bits program
Internal
CLOCK programming is activated
by the B2 + B3 logic state
CLOCK = 1:1 ratio
CLOCK : 1
Figure 25. Typical Clock Divider Synchronization
CLOCK: 4 rising edge
CLOCK
Divider
Figure 26. Basic Clock Divider and Level Shifter
B1
B0
B3
B2
CLK_IN
VCC
CRD_CLK
CRD_VCC
LEVEL SHIFTER
AND CONTROL
Programming
CRD_CLK Slope
NOTE: Bits [B0...B3] come from SPI data
Programming
CRD_CLK
Division
SYNC
ASYNC
SYNC
U1
DIGITAL_MUX
OUT
SEL
A
B
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