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參數(shù)資料
| 型號(hào)： | NCN6001DTBR2 |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 16/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTERFACE SMART CARD 20TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 應(yīng)用： | 智能卡 |
| 接口： | 微控制器 |
| 電源電壓： | 2.75 V ~ 5.5 V |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 安裝類型： | 表面貼裝 |
| 其它名稱： | NCN6001DTBR2OSDKR |
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NCN6001
http://onsemi.com
23
The system operates with a two cycles concept (all comments are referenced to Figure 17 and Figure 18):
1 Cycle 1
Q1 and Q4 are switched ON and the inductor L1 is charged by the energy supplied by the external battery.
During this phase, the pair Q2/Q3 and the pair Q5/Q6 are switched OFF.
The current flowing the two MOSFET Q1 and Q4 is internally monitored and will be switched OFF when
the Ipeak value (depending upon the programmed output voltage value) is reached. At this point, Cycle 1 is
completed and Cycle 2 takes place. The ON time is a function of the battery voltage and the value of the induct-
or network (L and Zr) connected across pins 10/11.
A 4
ms timeout structure ensures the system does run in a continuous Cycle 1 loop
2 Cycle 2
Q2 and Q3 are switched ON and the energy stored into the inductor L1 is dumped into the external load
through Q2. During this phase, the pair Q1/Q4 and the pair Q5/Q6 are switched OFF.
The current flow period is constant (900 ns typical) and Cycle 1 repeats after this time if the CRD_VCC
voltage is below the specified value.
When the output voltage reaches the specified value (1.8 V, 3.0 V or 5.0 V), Q2 and Q3 are switched OFF
immediately to avoid over voltage on the output load. In the meantime, the two extra NMOS Q5 and Q6 are
switched ON to fully discharge any current stored into the inductor, avoiding ringing and voltage spikes over
the system. Figure 18 illustrates the theoretical waveforms present in the DC/DC converter.
CRD_VCC Charged
Figure 18. Theoretical DC/DC Operating Waveforms
Ipeak
CRD_VCC
IL
Q5/Q6
Q2/Q3
Q1/Q4
Vripple
CRD_VCC Voltage Regulated
toff
ton
Charge CRD_VCC
Next CRD_VCC Charge
(Time is Not to Scale)
When the CRD_VCC is programmed to zero volt, or when
the card is extracted from the socket, the active pull down Q7
rapidly discharges the output reservoir capacitor, making
sure the output voltage is below 0.4 V when the card slides
across the ISO contacts.
Based on the experiments carried out during the
NCN6001 characterization, the best comprise, at time of
printing this document, is to use two 4.7
mF/10 V/
ceramic/X7R capacitors in parallel to achieve the
CRD_VCC filtering. The ESR will not extend 50 m
W over
the temperature range and the combination of standard parts
provide an acceptable –20% to +20% tolerance, together
with a low cost. Table 9 gives a quick comparison between
the most common type of capacitors. Obviously, the
capacitor must be SMD type to achieve the extremely low
ESR and ESL necessary for this application. Figure 19
illustrates the CRD_VCC ripple observed in the NCN6001
demo board depending upon the type of capacitor used to
filter the output voltage.
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