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參數(shù)資料
| 型號： | MT92101 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | IP Phone Processor(IP電話處理器（提供一個(gè)用于企業(yè)IP電話的解決方案）) |
| 中文描述： | IP電話處理器（的IP電話處理器（提供一個(gè)用于企業(yè)的IP電話的解決方案）） |
| 文件頁數(shù)： | 8/18頁 |
| 文件大?。?/td> | 174K |
| 代理商： | MT92101 |
MT92101
Preliminary Information
8
8x8). There are 8 row outputs, 6 column inputs and 2
programmable row/column IOs. Keypad scanning
involves reading the input register and interpreting it
based on the driven output state. Interrupts may be
masked on a per input basis. Key debounce, if
required, must be handled in software.
Interrupt Controller
The Interrupt Controller block manages all internally
generated CPU subsystem interrupts, plus 6 external
interrupts. It translates interrupts into regular IRQs
and fast, higher priority FIQs for the ARM-Thumb
CPU. A hardware priority scheme is used to
minimize interrupt latency. Each interrupt source may
be individually configured for the following:
polarity, active high or low;
enabled or disabled;
edge or level sensitivity;
interrupt type, IRQ or FIQ.
Watchdog Timer
The watchdog timer ensures that system lock-up
does not occur due to hardware or run-time software
errors. It is driven from the CPU subsystem clock
and contains a 32-bit primary counter and an 8-bit
secondary counter with prescaler. These counters
are user programmable, allowing control of the
watchdog CPU interrupt rate and of the time duration
in which this interrupt must be cleared. Any lock-up
situation would be cleared via a system reset
generated on time-out of the secondary counter.
The timer may be disabled for debug or similar
reasons via a control pin. An output is provided for
power-down or disabling of external functions during
watchdog time-out.
External Memory Interface
The External Memory Interface is the interface
between the on-chip B
μ
ILD bus and any external
memory and peripherals. It performs byte and half-
Word packing and sub-bus width writes to allow any
on-chip bus master to access 8- or 16-bit external
components. The external interface consists of 16
data pins, 22 address pins, 5 select pins, and 4
control/enable signals. It can address up to 4 Mbytes
of memory in 5 separate areas. Each area may be
independently configured for memory/peripheral type
and number of start/access/stop wait states (0 to
15). One area is dedicated to LCD control and
therefore, generates a strobe signal in place of the
normal chip select. Zero wait state operation at the
maximum specified operating frequency is supported
for devices having a 10nS access time or better.
Memory Interface (AOI - ARM-OAK Interface)
The Memory Interface allows the DSP to access the
CPU’s memory map, including all off-chip memory. A
fixed 16 kWord window in the DSP’s data memory
map may be mapped to any position within the
CPU’s memory map via a programmable BASE
ADDRESS. This window is termed ‘shared memory’.
Two separate BASE ADDRESS registers, one
accessible from the CPU and one from the DSP, are
implemented. The BASE ADDRESS is defined by
the contents of one of these registers, with selection
being controlled by the CPU.
In order to minimize latency, by default the Memory
Interface is the highest priority master on the B
μ
ILD
bus. However, the relative priorities of the Memory
Interface and each of the 2 DMA Controllers may be
fully
software
configured
Configuration Register.
via
the
System
Three modes of operation are supported for data
transfer across the AOI. The simplest mode, suitable
for limited data transfers at slow speed only,
generates wait states to the DSP during transfers. As
the DSP is typically operating faster than the CPU
this results in significant lost time to the DSP.
The second mode, READ AHEAD, stores the current
accessed address in a local register and returns data
from the previous access. The new data is then read
from memory and stored in the Memory Interface
ready for the next READ AHEAD cycle. This
mechanism avoids any DSP waits, at the expense of
a single sample latency, and is not suitable for
transferring large blocks of data.
The third mode, DMA, allows fast transfer and would
be the mechanism chosen for transferring larger
blocks of data. Blocks of data up to the full 16 kWord
shared memory area may be transferred with no
CPU or DSP intervention once the transfer is
initiated. A DSP interrupt is generated when the
transfer is complete.
Inter-processor communication through the AOI uses
a pair of registers: the CPU status register (writable
by the CPU only, readable by both processors) and
the DSP status register (writable by the DSP only,
readable by both processors). Each contains an
interrupt bit, 3 associated interrupt type bits, a ready
bit and 4 additional general purpose bits that may be
used to implement a polling mechanism.
The AOI transfers data between the asynchronous
clock
domains
of
the
implementation relies upon the DSP being clocked at
2
processors.
Its
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