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參數(shù)資料
| 型號(hào)： | MT92101 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | IP Phone Processor(IP電話處理器（提供一個(gè)用于企業(yè)IP電話的解決方案）) |
| 中文描述： | IP電話處理器（的IP電話處理器（提供一個(gè)用于企業(yè)的IP電話的解決方案）） |
| 文件頁數(shù)： | 5/18頁 |
| 文件大?。?/td> | 174K |
| 代理商： | MT92101 |
Preliminary Information
MT92101
5
Overview
The CPU subsystem supports guaranteed operation
at up to 25MHz and the DSP subsystem at up to
60MHz (60 MIPs) from a 3.3V power supply.
The device implements a flexible standard serial
interface
(TDM/Audio)
subsystem. The MT92101 is compatible with the
Mitel MT92303 dual CODEC, but may also be used
with most third party CODECs.
to
the
external
voice
Multiple simultaneous full duplex voice channels can
be supported. The number of channels is limited by
the available DSP or CPU MIPs and is typically
dependant upon the speech compression and echo
cancellation algorithms selected. Fax transmissions
may be relayed using a robust demodulation/
remodulation scheme.
The device has been fully optimised for low power
operation. It uses low power cell libraries, supports
software controlled low power modes for each
subsystem and macrocell and fully implements local
clock gating. The product is realised in three metal
layer, small geometry, 0.35
μ
m, CMOS technology.
The next generation product, the MT92102, will be
realised on very small geometry, four metal layer,
0.18
μ
m CMOS technology.
Note: The term ‘Word’ is used to represent 16- and
32-bit numbers within this document. When used in
the context of the DSP subsystem a Word is a 16-bit
number. When used in the context of the CPU
subsystem, a Word is a 32-bit number, with a 16-bit
number being a half-Word.
CPU Subsystem
The ARM-Thumb CPU subsystem integrates the
ARM7-Thumb CPU together with a range of
peripherals chosen for this application. The Mitel
B
μ
ILD architecture is used to provide a robust,
standard bus interface between each peripheral
block. Low power design techniques are used to
save power wherever possible.
The subsystem comprises the following blocks:
ARM-Thumb CPU,
Synchronous Serial Interface,
TDM Master Serial Interface,
General Purpose Timer,
Universal Asynchronous Receiver/Transmitter,
UART,
Quad Direct Memory Access Controller,
(DMAC),
USB Device Interface,
802.1 Ethernet Bridge and Dual MAC,
DES Accelerator,
32-bit General Purpose Input/Output,
Programmable Key Module Interface,
Keypad Scanner,
Interrupt Controller,
Watchdog Timer,
External Memory Interface,
Memory Interface (or ARM-OAK Interface, AOI),
Power Control,
B
μ
ILD Broadcast Module,
Boot ROM, 1024 Byte.
Simple external bus mastership is supported to allow
sharing of all external memory/peripheral resources.
On-chip resources are not available to external
masters.
ARM7-Thumb CPU
The ARM7-Thumb CPU is a high performance, low
power, 32-bit RISC processor core and include a
hardware instruction decompressor to support 16-bit
instruction half-Words. This core is based upon the
proven ARM7 and retains its full 32-bit address,
instruction and data Word widths. It contains a total
of 37 registers and supports 6 operating modes. The
core supports a fast response to interrupts (4 to 28
cycles) and all data processing instructions are fully
conditional. Operation with 16-bit instruction widths
is supported via a hardware decompressor operating
with zero timing overhead (3-stage pipeline
maintained). Code size in this mode is typically
reduced to 65% of the requirement for full 32-bit
instruction mode.
The core contains an ICEBreaker extension and
JTAG interface to support non-intrusive debug. This
JTAG interface also supports full boundary scan
access.
In the MT92101, the ARM-Thumb may be clocked at
up to 25MHz, although this is programmable (the
MT92102 will be clocked at up to 40MHz). A low
power sleep mode is supported.
Synchronous Serial Interface
The CPU subsystem has a Synchronous Serial
Interface, which typically controls a variety of devices
that employ a Synchronous Serial Interface.
Examples are serial EEPROMS, NVRAM, LCD and
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT92303 | 3.3V Quad Interface, Dual Codec(3.3V 四接口雙編解碼器（提供音頻到PCM的接口）) |
| MT9300 | Multi-Channel Voice Echo Canceller(多通道話音回聲消除器) |
| MT933 | () |
| MT93L16 | Low-Voltage Acoustic Echo Canceller(低電壓回聲消除器) |
| MTD2955V-1 | 30V N-Channel PowerTrench MOSFET |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT92210 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:1023 Channel Voice Over IP Processor |
| MT92210BG | 制造商:Microsemi Corporation 功能描述: |
| MT92220 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:1023 Channel Voice Over IP/AAL2 Processor |
| MT92220BG | 制造商:Microsemi Corporation 功能描述: |
| MT9234MU | 功能描述:MODEM V.92 DATA/FAX USB WORLD RoHS:是 類別:計(jì)算機(jī)，辦公室 - 元件，配件 >> 調(diào)制解調(diào)器 系列:MultiMobile™ USB 標(biāo)準(zhǔn)包裝:1 系列:MultiModem® ZBA 數(shù)據(jù)格式:V.34，V.92 波特率:- 電源電壓:- 安裝類型:臺(tái)式 封裝/外殼:5.7" L x 4.3" W x 1.0" H（145mm x 109mm x 25mm） 供應(yīng)商設(shè)備封裝:- 包裝:散裝 |
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