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參數(shù)資料
| 型號： | MT92101 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | IP Phone Processor(IP電話處理器（提供一個用于企業(yè)IP電話的解決方案）) |
| 中文描述： | IP電話處理器（的IP電話處理器（提供一個用于企業(yè)的IP電話的解決方案）） |
| 文件頁數(shù)： | 6/18頁 |
| 文件大?。?/td> | 174K |
| 代理商： | MT92101 |
MT92101
Preliminary Information
6
other display devices, CODEC and other voice
circuits. The interface is fully flexible and provides:
MICROWIRE
TM
Interface compatibility, to allow
interfacing to memory and peripheral devices
supporting this standard;
Serial Peripheral Interface (SPI) compatibility,
an interface found on certain Motorola, TI and
ST microcontrollers;
data transfer with either Byte or Word oriented
protocols, with the Word width being
configurable from 2 to 32 bits;
triple buffered Transmit and Receive Channels;
operation in either Interrupt or Polled mode;
support for up to 6 slave devices (i.e., 6 enable
signals, 1 clock and 1 bi-directional data);
fly-by support for single addressed DMA
transfers.
TDM Master Serial Interface
The TDM Master Serial Interface included in the
CPU subsystem is provided for use in tele-worker or
non-IP applications, where it becomes the main
system interface for voice data. The interface is
substantially the same as the TDM Audio interface
within the DSP subsystem, and is a fully flexible
multi-channel PCM based interface that provides:
a five pin interface (1 clock, RX and TX frame
syncs, input data and output data); frame syncs
and clock support programmable direction and
polarity;
single or multi-channel capability; the
multichannel facility allows time division
multiplexing of the serial bitstream into up to 32
channels. Any number of these channels can
be used for transmit or receive independently.
The CPU must supply data for the transmit
channels in the correct order and sort data from
the receive channel.
compatibility with Mitel ST-Bus and most PCM
busses;
transmit and receive sections can operate with
DMA from/to memory to reduce CPU
interaction;
inclusion of a compander circuit to support A-
law and
μ
-law interfaces; when enabled, the
companding operation is transparent to the
CPU. The compander may also be accessed
independantly by the CPU to allow separate
compression and expansion operations, in
parallel with companded or non-companded
serial IO.
General Purpose Timer
The CPU subsystem has a flexible general purpose
timer that may be used for timing multiple events.
Two identical independent timer/counter elements
are provided; each contains the following:
a 12-bit, variable prescaler generating the
counter clock;
a 32-bit fully programmable up/down timer/
counter;
multiple counter modes including free running,
halt-on-zero/overflow;
four 32-bit compare registers;
flexible interrupt generation from the timer and/
or compare registers;
PWM signal output option using main counter
and compare register 1.
Universal Asynchronous Rx/Tx, UART
A Universal Asynchronous Receiver Transmitter
(UART) is included in the CPU subsystem, providing
industry standard levels of support for full-duplex
asynchronous serial communications. It is typically
used for communication with a PC for configuration
or test purposes, but may also be used to implement
an IRDA port. Features of the UART include:
full duplex operation, independent transmit and
receive channels;
software configurable as either a DTE or DCE;
fully programmable baud rate selection derived
from subsystem clock; all standard baud rates
up to and including 153.6 and 230.4 kbit/s are
supported within acceptable margins;
theoretical limit for the interface of one half of
the subsystem clock frequency;
automatic baud rate and character format
detection for received data;
automated support of Hardware (RS-232C and
RS-232E) and Software Flow Control;
input filters for serial input data and modem
control inputs;
data formatting for 7 or 8 bit serial character, 1
or 2 stop bits, and even, odd, mark, space or no
parity;
line break detection/generation;
framing, overrun and parity errors, with interrupt
generation;
fly-by support for single addressed DMA
transfers.
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