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參數(shù)資料
| 型號(hào)： | MT92101 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | IP Phone Processor(IP電話處理器（提供一個(gè)用于企業(yè)IP電話的解決方案）) |
| 中文描述： | IP電話處理器（的IP電話處理器（提供一個(gè)用于企業(yè)的IP電話的解決方案）） |
| 文件頁(yè)數(shù)： | 7/18頁(yè) |
| 文件大?。?/td> | 174K |
| 代理商： | MT92101 |
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Preliminary Information
MT92101
7
Quad Direct Memory Access Controller, DMAC
The DMA Controllers allow data to be moved around
the subsystem with little CPU intervention. Each of
the 4 controllers contains a pair of sub-controllers,
each capable of managing a single addressed (fly-
by) DMA transfer between memory and an implicitly
addressed device, such as the UART. Alternatively, a
pair of sub-controllers may be used to perform dual
addressed transfers, where both source and
destination require address generation. A typical
application might allocate 4 sub-controllers to
support the Ethernet Bridge, leaving 2 controllers (or
4 sub-controllers) to support the UART, SSIO and
any memory to memory transfers. Each controller
supports the following:
transfer rates at up to 4 bytes per clock cycle,
single addressed, 2 bytes per cycle, dual
addressed;
transfer counts up to 64k items;
block and packet transfer modes;
chained transfers to support scatter-gather
operations;
hardware or software triggered transfers.
USB Device Interface
A standard USB interface for connection to a PC or
similar host is included, and has the following
features:
supports 8 programmable end points;
has a 16-byte FIFO buffer per end point.
802.1 Ethernet Bridge and Dual MAC
The 802.1 Ethernet Bridge and Dual MAC allows
connection of a desktop workstation (PC) to a LAN
through the IP telephone; one port connects to the
LAN, the other to the workstation. Using dual ports in
this way avoids the need for a dedicated LAN port for
the telephone and also reduces cable bulk.
The MAC ports support 10Base-T and 100Base-TX
Ethernet formats and have standard MII interfaces to
external PHYs. FIFO buffers are inserted in transmit
and receive paths between each MAC and the
switch. Input buffers are 3328 bytes deep to allow at
least 2 full packets to be accommodated, output
buffers are 1536 bytes deep, accommodating at least
1 full packet. The switch allows packet injection and
packet extraction for communication with the phone.
A watchdog counter allows the splitting of packet
transfers through the switch to avoid problems with
CPU/bus sharing.
DES Accelerator
The DES Accelerator is a hardware accelerator for
execution of the Data Encryption Standard (DES)
algorithm as defined in FIPS PUB 46-1, which is
equivalent to the Data Encryption Algorithm (DEA)
provided in ANSI x3.92-1981. Standard DES is
executed in just 16 clock cycles; cipher block
chaining (CBC) is supported and related DES
algorithms such as triple-DES and DES-X are also
supported.
32-bit General Purpose Input/Output
The General Purpose I/O is a set of up to 32 signals
that may be individually written to or read by the CPU
for general purpose control. Each signal is
programmable for direction (input or output) and pull-
resistors may be selectively disabled. Nine of these
signals may be configured such that they are
controlled directly from the DSP. Most General
Purpose I/O (GPIO) pins have internal pull-resistors
to either VIO or GND, split roughly equally; a few
GPIO pins have no pull-resistors. Therefore,
individual GPIO signals may be selected in order to
minimize
static
current
application, based upon the known external
conditions.
consumption
in
the
A number of the GPIO signals are multiplexed with
other functions in order to reduce pincount.
Multiplexing is controlled from the CPU and a
minimum of 14 GPIO signals are always available.
Programmable Key Module Interface
The Programmable Key Module Interface is a simple
serial interface intended to support a specialized
KEY and LED expansion port, which is required in
some systems. The features include the following:
a 4-wire interface: output clock, output frame
marker, output data and input data;
ability to send 16 bytes of control and receive
16 bytes of status information per frame;
a programmable clock divider from subsystem
clock, to facilitate low frequency operation
(typically 3kHz).
Because the PKM interface signals are mulitplexed
with GPIO pins and the interface may be powered
down, it may be disabled in systems where it is not
required.
Keypad Scanner
The flexible keypad interface supports keypad
configurations of up to 8x8 keys (e.g., 10x6, 9x7,
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