- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383646 > MT92101 (Mitel Networks Corporation) IP Phone Processor(IP電話處理器（提供一個用于企業(yè)IP電話的解決方案）) PDF資料下載
參數(shù)資料
| 型號： | MT92101 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | IP Phone Processor(IP電話處理器（提供一個用于企業(yè)IP電話的解決方案）) |
| 中文描述： | IP電話處理器（的IP電話處理器（提供一個用于企業(yè)的IP電話的解決方案）） |
| 文件頁數(shù)： | 12/18頁 |
| 文件大?。?/td> | 174K |
| 代理商： | MT92101 |
MT92101
Preliminary Information
12
Attempted access to internal program ROM (0x0000
to 0xEFFF) via a
movp
instruction will be detected
and blocked by a program protection mechanism, to
prevent unauthorised copying of embedded firmware.
All ROM may be programmed during wafer
metalisation to allow fast generation of code updates
and variants.
DSP Power Modes
The DSP subsystem supports three operating
modes: normal operation (or ACTIVE mode), low
power IDLE mode, and lowest power STOP mode.
The DSP is powered down in both IDLE and STOP
modes. In IDLE mode, the PLL remains active to
allow a fast switch to ACTIVE mode. In STOP mode,
the PLL is fully powered down and therefore, a time
delay is necessary to allow the PLL to lock and
settle. This time delay is automatically generated and
will be nominally 200
μ
s for a 40MHz master clock,
and proportionately longer for a slower clock.
Exit from IDLE mode is normally made via an
interrupt, although it may also occur via a system
reset, a soft DSP subsystem reset, or a CDI reset.
Exit from STOP mode normally is achieved under
control of the CPU via an OAK CONTINUE signal,
generated by the AOI. Alternatively, an external
interrupt, a system reset, a soft DSP subsystem
reset, or CDI reset may be used. Exit from STOP
mode is directly to ACTIVE mode. The OAK
CONTINUE
signal
ensures
recommences operation in exactly the same state
from which it entered STOP mode (i.e., all register
states are maintained).
that
the
DSP
Clock Provision and PLL Clock
Generation
The number of externally provided clocks is
minimised, while offering sufficient flexibility to cover
all possible applications. Two external, dedicated
clock sources are required:
MCLK provides the CPU Subsystem clock directly
and the TDM Clock via simple division. Two modes
of operation are possible as described below:
a) Internal TDM Clock
The master clock is limited to an integer multiple
of the required TDM clock frequency. The TDM
clocks are generated by dividing MCLK; the
ratio is programmable by the CPU (for the TDM
Master Interface) or the DSP (for the TDM
Audio Interface).
b) External TDM Clock
The master clock may be any frequency up to
40MHz. TDM clocks are input to the serial inter-
face clock pins.
Each USB clock may be driven from an off-chip logic
level source, or may be generated via an on-chip
crystal oscillator (i.e., requiring 2 pins per clock, 4
pins in total). MCLK must be active at all times to
allow the CPU to wake from STANDBY mode,
although UCLK may be externally disabled when the
USB is not being used, and when it is not selected as
the PLL clock source.
Master Clock (MCLK)
USB Clock (UCLK), fixed at 48.000 MHz
MCLK is typically used directly by the CPU
subsystem, but may be divided to lower power
consumption; division ratios of 2, 4, 8 and 16 are
supported.
On-core YRAM (2k)
0xFFFF
0xF800
OCEM Mem Map Registers (16w)
0xF7FF
0xF7F0
Reserved (2k-16w)
0xF7EF
0xF000
External Memory (16k)
0xEFFF
0xB000
Reserved
0xAFFF
0xA7E0
Mapped:
Off-chip
Mailbox (992w)
0xA7DF
0xA400
File IO (1k)
0xA3FF
0xA000
Data ROM (8k)
0x9FFF
0x8000
Shared Memory (16k)
0x7FFF
0x4000
Reserved (4k)
0x3FFF
0x3000
Mem Map Registers (4k)
0x2FFF
0x2000
Reserved (3k)
0x1FFF
0x1400
Off-core XRAM (3k)
0x13FF
0x0800
On-core XRAM (2k)
0x07FF
0x0000
Table 3. DSP Subsystem Data Memory Map
BIU Boot (2w)
0xFFFF
0xFFFE
Application/Patch RAM (4k–2w)
0xFFFD
0xF000
On Chip
Monitor (1k)
0xEFFF
0xEC00
On or Off Chip
Boot Code (64w)
0xEBFF
0xEBC0
On Chip
Application ROM (59k – 96w)
0xEBBF
0x0020
On or Off-chip
IPROG = 1 or 0
Interrupt Vectors (32w)
0x001F
0x0000
Table 4. DSP Subsystem Program Memory Map
相關PDF資料 |
PDF描述 |
|---|---|
| MT92303 | 3.3V Quad Interface, Dual Codec(3.3V 四接口雙編解碼器（提供音頻到PCM的接口）) |
| MT9300 | Multi-Channel Voice Echo Canceller(多通道話音回聲消除器) |
| MT933 | () |
| MT93L16 | Low-Voltage Acoustic Echo Canceller(低電壓回聲消除器) |
| MTD2955V-1 | 30V N-Channel PowerTrench MOSFET |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT92210 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:1023 Channel Voice Over IP Processor |
| MT92210BG | 制造商:Microsemi Corporation 功能描述: |
| MT92220 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:1023 Channel Voice Over IP/AAL2 Processor |
| MT92220BG | 制造商:Microsemi Corporation 功能描述: |
| MT9234MU | 功能描述:MODEM V.92 DATA/FAX USB WORLD RoHS:是 類別:計算機，辦公室 - 元件，配件 >> 調(diào)制解調(diào)器 系列:MultiMobile™ USB 標準包裝:1 系列:MultiModem® ZBA 數(shù)據(jù)格式:V.34，V.92 波特率:- 電源電壓:- 安裝類型:臺式 封裝/外殼:5.7" L x 4.3" W x 1.0" H（145mm x 109mm x 25mm） 供應商設備封裝:- 包裝:散裝 |
發(fā)布緊急采購，3分鐘左右您將得到回復。