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| 型號： | MT9088IG |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | TDM to Packet Processors |
| 中文描述： | TDM到分組處理器 |
| 文件頁數(shù)： | 95/97頁 |
| 文件大小： | 702K |
| 代理商： | MT9088IG |
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MT90880/1/2/3
Data Sheet
95
Zarlink Semiconductor Inc.
11.0 Glossary
ATM
Asynchronous Transfer Mode
CBR
Constant Bit Rate
CDP
Context Descriptor Protocol (used to indicate the contents of a packet stream or "context")
CES
Circuit Emulation Services
DBCES
Dynamic Bandwidth Circuit Emulation Services
DMA
Direct Memory Access
DPLL
Digital Phase Locked Loop
DSP
Digital Signal Processor
H.100/H.110
High capacity TDM backplane standards
HDLC
High-Level Data Link Control
H-MVIP
High-performance Multi-Vendor Integration Protocol (a TDM backplane standard)
IP
Internet Protocol
JTAG
Joint Test Algorithms Group (generally used to refer to a standard way of providing a board-level
test facility)
LAN
Local Area Network
MAC
Media Access Control
MII
Media Independent Interface
MIB
Management Information Base
PBSRAM
Pipelined Burst SRAM (a type of synchronous SRAM)
PCI
Peripheral Component Interconnect
PDV
Packet Delay Variation
PLL
Phase Locked Loop
PPP
Point to Point Protocol
PRBS
Pseudo-Random Bit Sequence
PSTN
Public Switched Telephone Circuit
QoS
Quality of Service
RMII
Reduced Media Independent Interface
SSRAM
Synchronous Static Random Access Memory
ST BUS
Standard Telecom Bus, a standard interface for TDM data streams
TDM
Time Division Multiplexing
WAN
Wide Area Network
WFQ
Weighted Fair Queuing
WRED
Weighted Random Early Discard
ZBT
Zero Bus Turnaround, a type of synchronous SRAM
0x
Denotes Hexadecimal notation
0b
Denotes binary notation
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