參數(shù)資料
型號(hào)： MT9088IG
廠商： Zarlink Semiconductor Inc.
英文描述： TDM to Packet Processors
中文描述： TDM到分組處理器
文件頁數(shù)： 81/97頁
文件大?。?/td> 702K
代理商： MT9088IG
MT90880/1/2/3
Data Sheet
81
Zarlink Semiconductor Inc.
Note: Typical figures are at 25
°
C and are for design aid only.
Typical characteristics are at 1.8 V core, 3.3 V I/O, 27
°
C and typical processing. The min and max values are defined over all process
conditions, from -40 to 125
°
C junction temperature, core voltage 1.65 to 1.95 and I/O voltage 3.0 and 3.6 V unless otherwise stated.
Note 1:
There are two analog PLLs with separate 1.8 V supplies. Each supply consumes current of I
DD_PLL
.
Recommended Operating Conditions -
Voltage measurements are with respect to ground (V
SS
) unless otherwise stated
.
Characteristics
Symbol
Min.
Typ.
Max.
Units
Test
Condition
Operating Temperature
T
OP
-40
25
+85
°
C
Junction temperature
T
J
-40
125
°
C
Package thermal resistance to
ambient
θ
JA
33
°
C/w
Positive Supply Voltage, I/O
V
DD_IO
3.0
3.3
3.6
V
Positive Supply Voltage, Core
V
DD_CORE
1.65
1.8
1.95
V
Positive Supply Voltage, Core
V
DD_PLL
1.65
1.8
1.95
V
Input Voltage Low - all inputs
V
IL
0.8
V
Input Voltage High
V
IH
2.0
V
DD_IO
V
Input Voltage High, 5 V tolerant inputs
V
IH_5 V
2.0
5.5
V
DC Characteristics
Characteristics
Symbol
Min.
Typ.
Max.
Units
Test Condition
Input Leakage
I
LEIP
±
1
μ
A
No pull up/down
V
DD
= 3.6 V
No pull up/down
V
DD
= 3.6 V
Output (High impedance) Leakage
I
LEOP
2
μ
A
Input Capacitance
Output Capacitance
Pullup Current
Pulldown Current
Core 1.8V supply current
PLL 1.8V supply current
I/O 3.3V supply current
C
IP
C
OP
I
PU
I
PD
2
4
pF
pF
μ
A
μ
A
mA
mA
m
Α
-33
33
220
Input at 0 V
Input at V
DD
I
DD_CORE
I
DD_PLL
I
DD_IO
1.25
Note 1
100
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