參數(shù)資料
型號(hào)： MT9088IG
廠商： Zarlink Semiconductor Inc.
英文描述： TDM to Packet Processors
中文描述： TDM到分組處理器
文件頁(yè)數(shù)： 33/97頁(yè)
文件大?。?/td> 702K
代理商： MT9088IG
MT90880/1/2/3
Data Sheet
33
Zarlink Semiconductor Inc.
Figure 14 - Packet to WAN Data Flow via Local Resource
PCI Interface to Packet Interface
The host CPU or other devices can use the MT9088x device to send data via the packet network. The data to
be sent is formatted into packets with the appropriate protocols in system memory. The DMA controller in the
MT9088x is programmed to fetch this information, and place it into the appropriate packet queue.
On transmission the packet is retrieved from memory by the Packet Formatter in the normal way, and passed to
the MAC for transmission.
Figure 15 - PCI to Packet Data Flow
Data Flow
Control Flow
Local Resource Pool
e.g. DSP pool
W
P
Packet Memory
Data Flow
Control Flow
W
P
Packet Memory
Host Processor
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