參數(shù)資料
型號： MT9088IG
廠商： Zarlink Semiconductor Inc.
英文描述： TDM to Packet Processors
中文描述： TDM到分組處理器
文件頁數(shù)： 85/97頁
文件大?。?/td> 702K
代理商： MT9088IG
MT90880/1/2/3
Data Sheet
85
Zarlink Semiconductor Inc.
10.1.2 Clock Master Mode
Table 32 - WAN Access Interface Timing - Master Mode
Figure 41 - WAN Bus Clock Master Mode Timing at 2.048 Mbs
Data format
Parameter
Symbol
Min.
Typ.
Max.
Units
Notes
ST-bus 8.192 Mbs mode
WAN_CLKO frequency
f
C16P
16.384
MHz
WAN_CLKO High Width
t
C16H
30
ns
WAN_CLKO Low Width
t
C16L
30
ns
ST-bus 2.048 Mbs mode
WAN_CLKO frequency
f
C4P
4.096
MHz
WAN_CLKO High Width
t
C4H
122
ns
WAN_CLKO Low Width
t
C4L
122
ns
Generic E1 2.048 Mbs
mode
WAN_CLKO frequency
f
C2P
2.048
MHz
WAN_CLKO High Width
t
C2H
244
ns
WAN_CLKO Low Width
t
C2L
244
ns
All modes
WAN_FRMO Output Delay
t
FOD
25
ns
WAN_STO Delay
t
STOD
25
ns
WAN_STI Setup Time
t
STIS
5
ns
WAN_STI Hold Time
t
STIH
5
ns
Channel 31 Bit 0
Channel 0 Bit 7
Channel 0 Bit 6
B0
B7
Ch 31 Bit 0
Ch 0 Bit 7
Ch 0 Bit 6
tSTOD
tSTOD
tFOD
tFOD
tC4H
tC4L
tSTIH
tSTIS
tSTIH
tSTIS
WAN_CLKO
WAN_FRMO
WAN_STI
WAN_STO
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