參數(shù)資料
型號(hào): MT90871AV
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Flexible 8K Digital Switch (F8KDX)
中文描述: TELECOM, DIGITAL TIME SWITCH, PBGA196
封裝: 15 X 15 MM, 1 MM PITCH, LBGA-196
文件頁數(shù): 36/65頁
文件大?。?/td> 639K
代理商: MT90871AV
MT90871
Data Sheet
36
Zarlink Semiconductor Inc.
Figure 18 - Frame Boundary Conditions, GCI - BUS Operation
13.2
Block Programming Register (BPR)
Address 0001h.
The block programming register stores the bit patterns to be loaded into the connection memories when the
Memory Block Programming feature is enabled. The BPE, LBPD2-0 and BBPD2-0 bits in the BPR register must
be defined in the same write operation.
The BPE bit is set HIGH, to commence the block programming operation. Programming is completed in one frame
period and may be be instigated at any time within a frame.The BPE bit returns to LOW to indicate the block
programming function has completed.
Frame Boundary
Pulse Width = 122ns,
Control Register Bit8 (FPW) = 0
Control Register Bit6 (C8IPOL) = 0
(e)
Pulse Width = 122ns,
Control Register Bit8 (FPW) = 0
Control Register Bit6 (C8IPOL) = 1
(f)
Pulse Width = 244ns,
Control Register Bit8 (FPW) = 1
Control Register Bit6 (C8IPOL) = 0
(g)
Pulse Width = 244ns,
Control Register Bit8 (FPW) = 1
Control Register Bit6 (C8IPOL) = 1
(h)
C8i_b
FP8i_b
C8i_b
FP8i_b
C8i_b
FP8i_b
C8i_b
FP8i_b
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