參數(shù)資料
型號(hào)： MT90871AV
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 路由/交換
英文描述： Flexible 8K Digital Switch (F8KDX)
中文描述： TELECOM, DIGITAL TIME SWITCH, PBGA196
封裝： 15 X 15 MM, 1 MM PITCH, LBGA-196
文件頁數(shù)： 31/65頁
文件大?。?/td> 639K
代理商： MT90871AV
Data Sheet
MT90871
31
Zarlink Semiconductor Inc.
12.0
Memory Address Mappings
The device contains two data memory blocks, one for received Backplane data and one for received Local
data. For all data rates the received data is converted to parallel format by internal serial to parallel converters
and stored sequentially in the relevant data memory.
12.1
Backplane Data Memory Bit Definition
The 8-bit Backplane Data Memory (BDM) has 4,096 positions. The locations are associated with the
Backplane input streams and channels. The address bits (A13:0) of the microprocessor define the addresses
of the streams and the channels. The BDM is configured as follows:
12.2
Local Data Memory Bit Definition
The 8-bit Local Data Memory (LDM) has 4,096 positions. The locations are associated with the Local input
streams and channels. The address bits of the microprocessor define the addresses of the streams and the
channels. The LDM is configured as follows:
12.3
Local Connection Memory Bit Definition
The Local Connection Memory (LCM) has 4,096 addresses of 16-bit words. Each address, accessed through
bits A13-A0 of the microprocessor port, is allocated to an individual Local output stream and channel. The bit
definition for each 16-bit word is presented in Table 10, LCM Bits for Local-to-Local and Backplane-to-Local
Switching. Bit LSRC selects the switch configuration for Backplane-to-Local or Local-to-Local. When the per-
Address Bit
Description
A14
Selects memory or register access
A13-A9
Stream address (0-15)
A8-A0
Channel address (0-255)
Notes:
1. Bit A14 must be high for accessing to data and connection memory positions. Bit A14 must
be low for accessing registers.
2. Channels 0 to 31 are used when serial stream is at 2.048Mb/s.
3. Channels 0 to 63 are used when serial stream is at 4.096Mb/s.
4. Channels 0 to 127 are used when serial stream is at 8.192Mb/s.
5. Channels 0 to 255 are used when serial stream is at 16.384Mb/s.
Table 7- Address Map for Data and Connection Memory Locations (A14=1)
Bit
Name
Description
15-8
Reserved
Set to a default value of 0
7-0
BDM
Backplane Data Memory
Backplane Input Channel Data
Table 8- Backplane Data Memory (BDM) Bits
Bit
Name
Description
15-8
Reserved
Set to a default value of 0
7-0
LDM
Local Data Memory
Local Input Channel Data
Table 9- Local Data Memory (LDM) Bits
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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MT90880B 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
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