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參數(shù)資料
| 型號： | MT90871AV |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 路由/交換 |
| 英文描述： | Flexible 8K Digital Switch (F8KDX) |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PBGA196 |
| 封裝： | 15 X 15 MM, 1 MM PITCH, LBGA-196 |
| 文件頁數(shù)： | 21/65頁 |
| 文件大?。?/td> | 639K |
| 代理商： | MT90871AV |
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Data Sheet
MT90871
21
Zarlink Semiconductor Inc.
outputs. Setting
BORS
to a HIGH state will configure the output streams
BSTo0-15
of the MT90871 to invoke
a high-impedance output on a per-channel basis.
The
BORS
pin is an asynchronous input and is expected
to be hard-wired for a particular system application,
although it may be driven under logic control if preferred.
4.2.1
BORS Set LOW.
The data (channel control bit) transmitted by
BCSTo0-1
replicates the Backplane Output Enable Bit (
BE
) of
the Backplane Connection Memory, with a LOW state indicating that the channel should be set to High
Impedance by external drivers. Refer to section 12.4 "Backplane Connection Memory Bit Definition".
The
BCSTo0-1
outputs transmit serial data (channel control bits) at 16.384Mb/s, with each bit representing the
per-channel high impedence state for specific streams. Eight output streams are allocated to each control line
as follows:
(See also
Pin Description
)
BCSTo0 outputs the channel control bits for streams BSTo0, 2, 4, 6, 8, 10, 12 and 14.
BCSTo1 outputs the channel control bits for streams BSTo1, 3, 5, 7, 9, 11, 13 and 15.
The Channel Control Bit location, within a frame period, for each channel of the Backplane output streams is
presented in
Table 3, BCSTo Allocation of Channel Control Bits to the Output Streams.
As an aid to the description, the channel control bit for a single channel on specific streams is presented, with
reference to Table 3:
1.
The Channel Control Bit corresponding to Stream 0, Channel 0,
BSTo0_Ch0,
is transmitted on
BCSTo0
and is advanced, relative to the Frame Boundary, by 10 periods of
C16o
, (i.e. clock period no. 2039).
The Channel Control Bit corresponding to Stream 14, Channel 0,
BSTo14_Ch0,
is transmitted on
BCSTo0
in advance of the Frame Boundary by three periods of output clock,
C16o
, (i.e. clock period
no. 2046). Similarly, the Channel Control Bit for
BSTo15_Ch0
is advanced relative to the Frame
Boundary by three periods of
C16o
, on
BCSTo1
.
2.
The
BCSTo0-1
outputs data at a constant data-rate of 16.384Mb/s, independent of the data-rate selected for
the individual output streams,
BSTo0-15
. Streams at data-rates lower than 16.384Mb/s will have the value of
the respective channel control bit repeated for the duration of the channel. The bit will be transmitted twice for
8.192Mb/s streams, four times for 4.096Mb/s streams and eight times for 2.048Mb/s streams. The channel
control bit is not repeated for 16.384Mb/s streams.
Examples are presented, with reference to Table 3:
3.
With stream
BSTo2
selected to operate at a data-rate of 2.048Mb/s, the value of the Channel Control Bit
for
Channel 0
will be transmitted during the
C16o
clock period nos. 2040, 2048, 8, 16, 24, 32, 40 and 48.
With stream
BSTo4
operated at a data-rate of 8.192Mb/s, the value of the Channel Control Bit for
Channel 1
will be transmitted during the
C16o
clock period nos. 9 and 17.
4.
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相關(guān)代理商/技術(shù)參數(shù) |
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| MT90871AV2 | 制造商:Microsemi Corporation 功能描述:PB FREE FLEXIBLE 8K DIGITAL SWITCH - Bulk 制造商:Microsemi Corporation 功能描述:IC, TDM SWITCH 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH F8KDX 196PBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH F8KDX 196PBGA |
| MT90880 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT90880B | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT90880B/IG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT90880BP1N | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
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