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參數(shù)資料
| 型號： | MT90520AG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| 中文描述： | ATM SEGMENTATION AND REASSEMBLY DEVICE, PBGA456 |
| 封裝： | 35 X 35 MM, 1.27 MM PITCH, PLASTIC, MS-034, BGA-456 |
| 文件頁數(shù)： | 132/180頁 |
| 文件大小： | 1736K |
| 代理商： | MT90520AG |
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MT90520
Data Sheet
132
Zarlink Semiconductor Inc.
GLOBAL_OAM_SEL
3
R/W
Global OAM Select.
When this bit is set, received OAM cells are kept for further processing. When this bit is
low, OAM cells are discarded.
EIGHT_N_SIXTEEN
4
R/W
8-bit mode/16-bit mode.
Selects between UTOPIA eight-bit (when set) and sixteen-bit (when cleared) operation.
LEVEL1_N_LEVEL2
5
R/W
Level1/Level2.
Selects between UTOPIA Level 1 (when set) and UTOPIA Level 2 (when cleared)
operation.
UKSEL
6
R/W
When this bit is set, cells which have unknown routing according to the look-up table are
placed in the Receive Data Cell Buffer; otherwise these cells are discarded.
CLAV_TRI_OVERRIDE
7
R/W
When set, this bit forces the CLAV signals to always drive a defined value. When this bit
is cleared, the CLAV signals become high impedance following a clock cycle in which
the MT90520 is not polled.
DATA_TRI_OVERRIDE
8
R/W
When set, this bit forces UTO_OUT_SOC and UTO_OUT_DATA to always drive defined
values. When this bit is low, the UTO_OUT_SOC and the UTO_OUT_DATA signals
become high impedance, as defined in the ATM Forum UTOPIA Level 2 specification.
PHY_N_ATM
9
R/W
PHY/ATM.
When set, the MT90520’s UTOPIA interface will operate in PHY mode; when the bit is
cleared, the MT90520’s UTOPIA interface will operate in ATM mode.
DEVICE_ADDRESS
14:10
R/W
Defines the address of the MT90520 device used to compare to the UTO_IN_ADD and
UTO_OUT_ADD buses when operating in MPHY mode.
Note:
Only addresses 00h to
1Eh are valid.
UTO_CLK_
CONFIGURED
15
R/W
The user must set this bit at least one clock cycle after the UTO_CLK_SEL bit has been
programmed.
For normal operation of the UTOPIA port, this bit must be set and
must not be cleared.
This bit should be set only once the UTOPIA is fully programmed (including the LUT,
which should be cleared (all the entries set to 0003h) even if not used).
Address: 4002 (Hex)
Label: UNCB
Reset Value: 0000 (Hex)
Label
Bit
Position
Type
Description
M
3:0
R/W
M least-significant bits of the VPI used for external memory look-ups.
The valid range for
this value is 0 to 12.
N
8:4
R/W
N least-significant bits of the VCI used for external memory look-ups.
The valid range for
this value is 4 to 16.
BACK_TO_BACK
_DISABLED
9
R/W
When asserted this bit will force the RX UTOPIA ATM state machine to pause after each
cell reception by driving the UTO_IN_ENBATM_ CLAVPHY signal to ‘1’
Reserved
15:10
R/O
Always reads “0000_00”.
Note:
The contents of this register are used to determine how many bits of the cell header are used to form the look-up table addresses.
The user selects up to 16 of the bits of the GFC/VPI and VCI fields to be used for the look-up table search. A minimum of 4 bits (from the
VCI) and a maximum of 16 bits (all from the VCI or from a combination of both the VCI and VPI) of the header must be used for searches.
Table 60 - UTOPIA Number of Concatenated Bits Register
Address: 4000 (Hex)
Label: UCR
Reset Value: 0004 (Hex)
Label
Bit
Position
Type
Description
Table 59 - UTOPIA Configuration Register
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90520AG2 | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90528 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG2 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90710 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:High-Speed Isochronous Multiplexer |
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