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MT90520
Data Sheet
47
Zarlink Semiconductor Inc.
Underrun Detection in SDT Mode
The SDT TDM reassembly process reads data which was written to the SDT Reassembly Circular Buffers by the
SDT RX_SAR block. Because the SDT RX_SAR and the TDM module don’t operate at the same rate (i.e., data is
written to the buffers based on the cell arrival rate while data is read from the buffers at a constant rate determined
by the TDM output clock rate), there is a possibility of underruns. The SDT TDM reassembly process therefore
performs underrun detection. The SDT TDM reassembly process compares the two most significant bits of the
TDM channel’s read pointer with the two bits called “turn” which are stored in the SDT Reassembly Circular Buffer
entries:
1- If the comparison is true
(i.e., 2 MSB of the read pointer = turn)
, there is no underrun.
2- If the previous comparison is false, a second comparison
(2 MSB of the read pointer = turn + 1 or 2 MSB of
the read pointer = turn + 2)
is performed. If this comparison is true, a simple underrun has occurred. The
REPLAY_NSILENCE bit is checked: if it is set, the reassembly process keeps reading (old data) from the circular
buffer. If it is not set, a silence byte (as configured in Main TDM Control Register 1) is written to the port’s TDM
Output Buffer for the underrunning channel. If the SU bit is set in the TDM SDT Reassembly Control Structure, a
simple underrun is reported in the port’s TDM Control Register 4.
3- If the two previous comparisons are false, a third comparison
(2 MSB of the read pointer = turn + 3)
is
performed. If this comparison is true, a permanent underrun has occurred. The REPLAY_NSILENCE bit is checked:
if it is set, the reassembly process keeps reading (old data) from the circular buffer. If it is not set, a silence byte (as
configured in Main TDM Control Register 1) is written to the port’s TDM Output Buffer for the underrunning channel.
If the PU bit is set in the TDM SDT Reassembly Control Structure, a permanent underrun is reported in the port’s
TDM Control Registers 4, and 5 or 6.
Once a permanent underrun is detected on a TDM channel, underrun data (silence or old buffer data) will be sent
out on DSTo[p] until the channel’s permanent underrun bit is cleared in TDM5_Pp or TDM6_Pp.
Underrun Considerations
The SDT TDM reassembly process internal to the MT90520 performs underrun detection. Underruns are declared
when the receive circular buffer does not have valid data to play out onto the TDM bus. The underrun detection is
performed on a per channel basis for each of the up to 32 channels on a TDM port. The underrunning channels are
reported TDM Control Register 4, TDM Control Register 5 and TDM Control Register 6.
Each active channel in a VC may be used independently to perform underrun detection. For example, in a 10
channel VC, each of the 10 channels may have their underrun detection activated. Thus all 10 channels are
programmed to report underrun to the host processor. However the same functionality may be achieved by
reporting underrun on a single channel in the VC, thereby reducing the amount of work required of the host
processor and the number of interrupts generated. Given that all the channels are part of the same VC and will
experience the same cell loss and CDV, when one channel underruns, they all underrun. So, for the example given,
one channel would have its underrun detection activated and the 9 other channels would have their underrun
detection disabled.
Internal to the MT90520 the underrun detection mechanism is dependent on the active channel order of the output
TDM bus DSTo. Underrun is mis-reported on any channel (x) for which an upper channel (x+4) is not active on the
same TDM port. As an example, channel 5 underrun status would be mis-reported if channel 9 of the same output
TDM port was inactive. Given this operation it is suggested that underrun detection be enabled only on receive
channels in a VC that are not mis-reporting underrun. Those channels which are mis-reporting underrun would
have their underrun detection disabled. Note again that only a single channel per receive VC is required to have its
underrun detection enabled to provide the equivalent functionality as all receive channels in a VC detecting
underrun.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT9072 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AB | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AV | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90820 | Large Digital Switch |
| MT90820AL | Large Digital Switch |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90520AG2 | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90528 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG2 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90710 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:High-Speed Isochronous Multiplexer |
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